Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

Community created parallella projects

An implementation of DisplayPort protocol for FPGAs

Library of VHDL components that are useful in larger designs.

TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.

FPGA-based Multi-Effects system for the electric guitar

Xilinx Deep Learning IP

A comparison of 1st and 2nd order sigma delta DAC for FPGA

Software Defined Radio receiver in Marsohod2 Altera Cyclone III board

Sending UDP packets out over a Gigabit PHY with an FPGA.

Artificial Neural Network on Altera DE2

It is a GPIO interrupt example for xilinx ZYNQ FPGA.

Various HDL designs for the Numato Labs/Timvideos HDMI2USB FPGA board

Deep Learning Processing Unit (DPU IP) integration with Application Processing Unit (APU) using (Zynq-7000 PS) in Xilinx Vivado Design Suite

Example code for the Numato Opsis board, the first HDMI2USB production board.

用ISE实现高斯分布随机数生成器，使用Box-Muller的方法，含有Matlab说明程序

Asynchronous FIFO using verilog

VHDL toy implementation of the Google TPU architecture.