🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…

VUnit is a unit testing framework for VHDL/SystemVerilog

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

ZPUino HDL implementation

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

cryptography ip-cores in vhdl / verilog

VHDL library for 10 GbE supporting UDP/IP, ARP, ICMP and DHCP