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Showing results

A modern Jellyfin client built with Expo

TypeScript 4,640 214 Updated Mar 24, 2026

A Python library and CLI tool for decrypting encrypted SPICE model files, enabling engineers to use lawfully obtained models in any simulator.

Python 139 9 Updated Mar 19, 2026

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

Python 500 92 Updated Mar 24, 2026

Generate VHDL RTL that implements a register block from compiled SystemRDL input.

Python 12 5 Updated Mar 15, 2026

file copy using io_uring

C++ 4 Updated Jan 7, 2026

Working example of a yocto setup without unnecessary complications

BitBake 190 32 Updated Oct 9, 2025

Open Source Embedded ADS-B Receiver

C++ 232 27 Updated Mar 23, 2026

A fast and customizable music and podcast downloader.

Python 2,360 228 Updated Sep 18, 2024

Universal utility for programming FPGA

C++ 1,580 332 Updated Mar 25, 2026

Mstflint - an open source version of MFT (Mellanox Firmware Tools)

C 245 117 Updated Mar 24, 2026

Antmicro's fast, vendor-neutral DMA IP in Chisel

Scala 130 27 Updated Mar 6, 2026

Scientific measurement library for instruments, experiments, and live-plotting

Python 725 432 Updated Mar 20, 2026

An alternative PCB pawprint for the Tag-Connect TC2030 pogo pin programming cable

137 3 Updated Oct 28, 2024

Open source Linux device drivers

Python 123 65 Updated Jun 19, 2025

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

Verilog 1,321 35 Updated Mar 12, 2026

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus

VHDL 72 12 Updated Feb 12, 2026

Control and status register code generator toolchain

Python 182 37 Updated Mar 24, 2026

Libssh SSH client & server port to ESP32 Arduino library

C 355 50 Updated Feb 11, 2026

Open screen control for AOOSTAR WTR MAX and GEM12+ PRO

Rust 118 11 Updated Sep 17, 2025

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

Verilog 867 149 Updated Dec 6, 2024

DIY ADSB Receiver

C 14 2 Updated Oct 28, 2024

✈️ Multi-functional, compatible DIY general aviation proximity awareness system

C 963 250 Updated Mar 25, 2026

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

Verilog 1,214 95 Updated Mar 23, 2026

This project provides an API for optimizing battery schedules using MQTT-based forecasts and a linear optimization algorithm.

Python 1 Updated Apr 5, 2025
VHDL 2 1 Updated Jul 17, 2025

Lightweight packet protocol structure for multi-device communication focused on RS-485

C 351 72 Updated Jan 22, 2026

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Verilog 271 45 Updated Mar 26, 2022

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL 703 68 Updated Dec 14, 2025

Compiler for multiple programming models (SYCL, C++ standard parallelism, HIP/CUDA) for CPUs and GPUs from all vendors: The independent, community-driven compiler for C++-based heterogeneous progra…

C++ 1,807 211 Updated Mar 23, 2026
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