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CERN
- Geneva, Switzerland
Stars
A modern Jellyfin client built with Expo
A Python library and CLI tool for decrypting encrypted SPICE model files, enabling engineers to use lawfully obtained models in any simulator.
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
Generate VHDL RTL that implements a register block from compiled SystemRDL input.
Working example of a yocto setup without unnecessary complications
A fast and customizable music and podcast downloader.
Universal utility for programming FPGA
Mstflint - an open source version of MFT (Mellanox Firmware Tools)
Antmicro's fast, vendor-neutral DMA IP in Chisel
Scientific measurement library for instruments, experiments, and live-plotting
An alternative PCB pawprint for the Tag-Connect TC2030 pogo pin programming cable
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus
Control and status register code generator toolchain
Libssh SSH client & server port to ESP32 Arduino library
Open screen control for AOOSTAR WTR MAX and GEM12+ PRO
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…
A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1
This project provides an API for optimizing battery schedules using MQTT-based forecasts and a linear optimization algorithm.
Lightweight packet protocol structure for multi-device communication focused on RS-485
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Compiler for multiple programming models (SYCL, C++ standard parallelism, HIP/CUDA) for CPUs and GPUs from all vendors: The independent, community-driven compiler for C++-based heterogeneous progra…