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scr1
scr1 PublicForked from syntacore/scr1
SCR1 is an open-source RISC-V compatible MCU core
SystemVerilog
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fpga-sdk-prj
fpga-sdk-prj PublicForked from syntacore/fpga-sdk-prj
FPGA-based SDK projects for SCRx cores
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wb_riscvscale
wb_riscvscale PublicForked from heshamelmatary/wb_riscvscale
This is a wishbone compliant RISCV Vscale core intended to run part of FuseSoC project with other (open)cores.
Verilog
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