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  1. alexorlov.github.io alexorlov.github.io Public

  2. scr1 scr1 Public

    Forked from syntacore/scr1

    SCR1 is an open-source RISC-V compatible MCU core

    SystemVerilog

  3. scr1-sdk scr1-sdk Public

    Forked from syntacore/scr1-sdk

    open-source SDK for SCR1 core

    C

  4. fpga-sdk-prj fpga-sdk-prj Public

    Forked from syntacore/fpga-sdk-prj

    FPGA-based SDK projects for SCRx cores

    Verilog

  5. wb_riscvscale wb_riscvscale Public

    Forked from heshamelmatary/wb_riscvscale

    This is a wishbone compliant RISCV Vscale core intended to run part of FuseSoC project with other (open)cores.

    Verilog

  6. lufa lufa Public

    Forked from abcminiuser/lufa

    LUFA - the Lightweight USB Framework for AVRs.

    C