Skip to content
View aolofsson's full-sized avatar
🏃‍♂️
🏃‍♂️

Highlights

  • Pro

Organizations

@parallella @adapteva @zeroasiccorp @siliconcompiler

Block or report aolofsson

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast

Python 64 12 Updated Jul 29, 2026

Boilerplate codebase for Embedded FPGA kernel development via YosysHQ & BSV

Bluespec 5 1 Updated Aug 4, 2026
Python 3 Updated Jul 20, 2026
Tcl 17 2 Updated Jul 9, 2026

A curated list of open-source resources for IC design.

Python 2 Updated Aug 3, 2026

AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.

Verilog 16 6 Updated Aug 4, 2026
Verilog 3 Updated Jul 9, 2026

WaveCrux public beta — issue tracking, help, and the public test-fixture corpus. No application source.

Verilog 8 Updated Aug 3, 2026

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SystemVerilog 12,801 1,227 Updated Aug 18, 2024
Verilog 65 7 Updated Jul 13, 2026

High quality and composable RTL libraries in SystemVerilog

SystemVerilog 47 7 Updated Aug 3, 2026

📸 ADCs for 100,000 FPS imaging

Python 8 Updated Aug 3, 2026

An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics

SourcePawn 18 1 Updated Jul 31, 2026
Python 7 1 Updated Jun 8, 2026

Sudoless Apple Silicon system monitor (native SwiftUI GUI) with ANE / Media Engine / memory-bandwidth tracking

Swift 812 50 Updated Jul 29, 2026

Param + EDA — a hierarchical configuration system for EDA tooling: config-folder tree with parent/child scoping, lazy variable substitution, and JSON-backed load/save.

C++ 2 Updated Jun 28, 2026

Universal bidirectional grammar-driven engine for EDA file formats. One grammar drives parse + save for GDSII, LEF, DEF, Tcl.

C++ 8 1 Updated Jul 14, 2026

An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled to an open RISC-V-native LPU accelerator. Apache-2.0 RTL, CER…

SystemVerilog 22 3 Updated Jun 14, 2026

[DEPRECATED → wrightca1/edgenos] AS4610-54T bring-up, now part of the unified multi-arch/multi-ASIC EdgeNOS repo

C 35 1 Updated Jun 29, 2026

Zero Board Computer semihosting device reference implementation

C 11 Updated Jun 13, 2026

Gati Accelerates Your CNN Algorithms!

Verilog 24 5 Updated Jun 12, 2026

The SoC for the introduction to chip design course spring 2026

Jupyter Notebook 19 2 Updated May 22, 2026

CoreSmith is a Prompt to GDS Agentic Flow

Python 34 4 Updated Aug 3, 2026

A library of agent skills for CAD, CAE and CAM

JavaScript 12,700 1,342 Updated Aug 3, 2026

A fully featured audio DSP firmware for the Raspberry Pi Pico (RP2040) and Pico 2 (RP2350). Official Discord: https://discord.gg/RCyqxAQ5xS

C 1,134 64 Updated Aug 4, 2026

FPGA Developer board repository

Python 23 3 Updated Jul 4, 2026

ARCH hardware description language and compiler

Rust 73 6 Updated Aug 3, 2026

Tachyon, IPC/RPC primitive.

C++ 300 14 Updated Jun 23, 2026
Next