Tags: cwshu/qemu
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cover-letter: v4: Implements RISC-V Worlds CPU extension This patchset implements 5 RISC-V Worlds CPU extensions in RISC-V Worlds spec and wgChecker device in legacy WorldGuard spec v0.4. RISC-V Worlds spec could be found here: https://github.com/riscv/riscv-worlds Legacy WG v0.4 spec could be found here: https://lists.riscv.org/g/security/attachment/711/0/worldguard_rvia_spec-v0.4.pdf To enable RISC-V Worlds in QEMU, pass "worlds=on" as machine parameter to virt machine. It enables both RV Worlds CPU CSRs to apply WID of CPU and wgCheckers on the DRAM, FLASH, and UART to protect these resources. This patchset contains 5 parts: 1. Commit 1 ~ 2: Bugfix of IOMMUMemoryRegion 2. Commit 3 ~ 4: Extend IOMMUMemoryRegion and MemTxAttr for RV Worlds support 3. Commit 5 ~ 14: Add RISCV Worlds global device and CPU extensions 4. Commit 15 ~ 18: Add WG checker device 5. Commit 19: Add WG support to the virt machine QEMU code can be found at [1] [1] https://github.com/cwshu/qemu/tree/riscv-wg-v3 Changed since v3: - Aligned with latest RISC-V World spec. Add 2 CPU extensions - TODO Changed since v2: - Fix the issues in v2 series as suggested by Daniel Henrique Barboza - Explain the changes of 'reserved' fields in MemTxAttr - Make isa_edata_arr in order - Replace qemu_get_cpu() with cpu_by_arch_id(). Do the clean exit when return NULL. - Simplify the machine option checking via 'object_property_get_bool' - Add the minor fixes and improvements to the wgChecker: - Increase the maximum number of region of a wgchecker from 16 to 64 - Clear the IRQ pending of wgchecker when writing to `errcause.ip` - Do the TLB flush when resetting the wgchecker - Improve the trace message Changed since v1: - Remove the assertion of 4k sections limitation. Remove iotlb_to_section() and rename 'xlat_section' to 'xlat'. - Fix RST issue and typo in virt machine doc Changed since RFCv1: - Rebase to latest QEMU (v10.0.0-rc3) - Add the description of HW config and CPU option of WG in the virt machine documentation - Expose CPU options of WG after WG CPU code has been implemented - Change 'mwid' and 'mwidlist' options to experimental options - Change 'world_id' to unsigned int type + bit field.
cover-letter: v4: Implements RISC-V Worlds CPU extension This patchset implements 5 RISC-V Worlds CPU extensions in RISC-V Worlds spec and wgChecker device in legacy WorldGuard spec v0.4. RISC-V Worlds spec could be found here: https://github.com/riscv/riscv-worlds Legacy WG v0.4 spec could be found here: https://lists.riscv.org/g/security/attachment/711/0/worldguard_rvia_spec-v0.4.pdf To enable RISC-V Worlds in QEMU, pass "worlds=on" as machine parameter to virt machine. It enables both RV Worlds CPU CSRs to apply WID of CPU and wgCheckers on the DRAM, FLASH, and UART to protect these resources. This patchset contains 5 parts: 1. Commit 1 ~ 2: Bugfix of IOMMUMemoryRegion 2. Commit 3 ~ 4: Extend IOMMUMemoryRegion and MemTxAttr for RV Worlds support 3. Commit 5 ~ 14: Add RISCV Worlds global device and CPU extensions 4. Commit 15 ~ 18: Add WG checker device 5. Commit 19: Add WG support to the virt machine QEMU code can be found at [1] [1] https://github.com/cwshu/qemu/tree/riscv-wg-v3 Changed since v3: - TODO Changed since v2: - Fix the issues in v2 series as suggested by Daniel Henrique Barboza - Explain the changes of 'reserved' fields in MemTxAttr - Make isa_edata_arr in order - Replace qemu_get_cpu() with cpu_by_arch_id(). Do the clean exit when return NULL. - Simplify the machine option checking via 'object_property_get_bool' - Add the minor fixes and improvements to the wgChecker: - Increase the maximum number of region of a wgchecker from 16 to 64 - Clear the IRQ pending of wgchecker when writing to `errcause.ip` - Do the TLB flush when resetting the wgchecker - Improve the trace message Changed since v1: - Remove the assertion of 4k sections limitation. Remove iotlb_to_section() and rename 'xlat_section' to 'xlat'. - Fix RST issue and typo in virt machine doc Changed since RFCv1: - Rebase to latest QEMU (v10.0.0-rc3) - Add the description of HW config and CPU option of WG in the virt machine documentation - Expose CPU options of WG after WG CPU code has been implemented - Change 'mwid' and 'mwidlist' options to experimental options - Change 'world_id' to unsigned int type + bit field.
cover-letter: v4: Implements RISC-V Worlds CPU extension This patchset implements 5 RISC-V Worlds CPU extensions in RISC-V Worlds spec and wgChecker device in legacy WorldGuard spec v0.4. RISC-V Worlds spec could be found here: https://github.com/riscv/riscv-worlds Legacy WG v0.4 spec could be found here: https://lists.riscv.org/g/security/attachment/711/0/worldguard_rvia_spec-v0.4.pdf To enable RISC-V Worlds in QEMU, pass "worlds=on" as machine parameter to virt machine. It enables both RV Worlds CPU CSRs to apply WID of CPU and wgCheckers on the DRAM, FLASH, and UART to protect these resources. This patchset contains 5 parts: 1. Commit 1 ~ 2: Bugfix of IOMMUMemoryRegion 2. Commit 3 ~ 4: Extend IOMMUMemoryRegion and MemTxAttr for RV Worlds support 3. Commit 5 ~ 14: Add RISCV Worlds global device and CPU extensions 4. Commit 15 ~ 18: Add WG checker device 5. Commit 19: Add WG support to the virt machine QEMU code can be found at [1] [1] https://github.com/cwshu/qemu/tree/riscv-wg-v3 Changed since v3: - TODO Changed since v2: - Fix the issues in v2 series as suggested by Daniel Henrique Barboza - Explain the changes of 'reserved' fields in MemTxAttr - Make isa_edata_arr in order - Replace qemu_get_cpu() with cpu_by_arch_id(). Do the clean exit when return NULL. - Simplify the machine option checking via 'object_property_get_bool' - Add the minor fixes and improvements to the wgChecker: - Increase the maximum number of region of a wgchecker from 16 to 64 - Clear the IRQ pending of wgchecker when writing to `errcause.ip` - Do the TLB flush when resetting the wgchecker - Improve the trace message Changed since v1: - Remove the assertion of 4k sections limitation. Remove iotlb_to_section() and rename 'xlat_section' to 'xlat'. - Fix RST issue and typo in virt machine doc Changed since RFCv1: - Rebase to latest QEMU (v10.0.0-rc3) - Add the description of HW config and CPU option of WG in the virt machine documentation - Expose CPU options of WG after WG CPU code has been implemented - Change 'mwid' and 'mwidlist' options to experimental options - Change 'world_id' to unsigned int type + bit field.
cover-letter: v4: Implements RISC-V World CPU extension This patchset implements 5 RISC-V World CPU extensions in RISC-V World spec and wgChecker device in legacy WorldGuard spec v0.4. RISC-V World spec could be found here: https://github.com/riscv/riscv-worlds Legacy WG v0.4 spec could be found here: https://lists.riscv.org/g/security/attachment/711/0/worldguard_rvia_spec-v0.4.pdf To enable RISC-V World in QEMU, pass "world=on" as machine parameter to virt machine. It enables both RV World CPU CSRs to apply WID of CPU and wgCheckers on the DRAM, FLASH, and UART to protect these resources. This patchset contains 5 parts: 1. Commit 1 ~ 2: Bugfix of IOMMUMemoryRegion 2. Commit 3 ~ 4: Extend IOMMUMemoryRegion and MemTxAttr for WG support 3. Commit 5 ~ 14: Add WG global device and CPU extensions 4. Commit 15 ~ 18: Add WG checker device 5. Commit 19: Add WG support to the virt machine QEMU code can be found at [1] [1] https://github.com/cwshu/qemu/tree/riscv-wg-v3 Changed since v3: - TODO Changed since v2: - Fix the issues in v2 series as suggested by Daniel Henrique Barboza - Explain the changes of 'reserved' fields in MemTxAttr - Make isa_edata_arr in order - Replace qemu_get_cpu() with cpu_by_arch_id(). Do the clean exit when return NULL. - Simplify the machine option checking via 'object_property_get_bool' - Add the minor fixes and improvements to the wgChecker: - Increase the maximum number of region of a wgchecker from 16 to 64 - Clear the IRQ pending of wgchecker when writing to `errcause.ip` - Do the TLB flush when resetting the wgchecker - Improve the trace message Changed since v1: - Remove the assertion of 4k sections limitation. Remove iotlb_to_section() and rename 'xlat_section' to 'xlat'. - Fix RST issue and typo in virt machine doc Changed since RFCv1: - Rebase to latest QEMU (v10.0.0-rc3) - Add the description of HW config and CPU option of WG in the virt machine documentation - Expose CPU options of WG after WG CPU code has been implemented - Change 'mwid' and 'mwidlist' options to experimental options - Change 'world_id' to unsigned int type + bit field.
hw/riscv: virt: Add fdt support of WG Add fdt support of wgcpus and wgcheckers. Signed-off-by: Jim Shu <jim.shu@sifive.com>
hw/riscv: virt: Add fdt support of WG Add fdt support of wgcpus and wgcheckers. Signed-off-by: Jim Shu <jim.shu@sifive.com>
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