Like Prometheus, but for logs.

Test suite designed to check compliance with the SystemVerilog standard.

A code coverage tool for Rust projects

LL(k) and LALR(1) parser generator for Rust

Empowering everyone to build reliable and efficient software.

⚓ GROWI - Team collaboration software using markdown

Let's write RISC-V CPU in Veryl!

A cross-platform, OpenGL terminal emulator.

Code generation tool for control and status registers

Gain deeper insights into your favourite open-source repositories. Explore star trends showing daily stars and go beyond the 40k-star limit.

Language Server Protocol implementation for Rust based on Tower

Cargo subcommand `release`: everything about releasing a rust crate.

Translation support for mdbook. The plugins here give you a structured way to maintain a translated book.

A terminal workspace with batteries included

Cargo subcommand to easily use LLVM source-based code coverage (-C instrument-coverage).

🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl

RSD: RISC-V Out-of-Order Superscalar Processor

bluecore - risc-v cpu

Synthesizeable Veryl Arbitration Tree

Filelist generator

Graph the number of crates that depend on your crate over time

Rust library for reading the Linux procfs filesystem

GitHub Action for continuous benchmarking to keep performance

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Basic Common Modules

This crate provides useful tools to generate multiple readable passwords, as well as analyze and score them.