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Synthesizeable Veryl Arbitration Tree

Language Server Protocol implementation for Rust based on Tower

In love with Atalanta

🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl

Let's write RISC-V CPU in Veryl!

A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding

bluecore - risc-v cpu

pzbcm written in veryl

Translation support for mdbook. The plugins here give you a structured way to maintain a translated book.

Kuroko is a small tool to convert from EMF to PDF. A typical use of this tool is to create PDF files from PowerPoint/Excel for use in LaTeX. You can download a pre-compiled binary from https://gith…

An asynchronous, runtime data feedable terminal paging library for Rust

Basic Common Modules

Filelist generator

LL(k) and LALR(1) parser generator for Rust

Cargo subcommand to easily use LLVM source-based code coverage (-C instrument-coverage).

「Rustでもわかるシステムプログラミング」

A terminal workspace with batteries included

monolish: MONOlithic LInear equation Solvers for Highly-parallel architecture

Empowering everyone to build reliable and efficient software.

Your Little Cargo Registry

Library of High Precision Sparse Matrix Operations Accelerated by SIMD

Useful UVM extensions

Determines the modules declared and instantiated in a SystemVerilog file

A SystemVerilog source file pickler.