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  • PEZY Computing K.K.
  • Kanagawa, Japan
  • 04:53 (UTC +09:00)
  • X @dalance1982

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@pezy-computing

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8 stars written in SystemVerilog
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RSD: RISC-V Out-of-Order Superscalar Processor

SystemVerilog 1,122 109 Updated Oct 23, 2025

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog 346 84 Updated Nov 5, 2025

Network on Chip Implementation written in SytemVerilog

SystemVerilog 192 52 Updated Aug 27, 2022

Basic Common Modules

SystemVerilog 44 8 Updated Aug 25, 2025

Useful UVM extensions

SystemVerilog 25 6 Updated Jul 10, 2024
SystemVerilog 20 3 Updated Sep 26, 2025

In love with Atalanta

SystemVerilog 15 4 Updated Feb 28, 2025
SystemVerilog 10 2 Updated May 27, 2025