🕹 Add/Remove games to "Data Frog Y2-HD (568 in 1)" console or to similar kind of consoles

Cyclone V bitstream reverse-engineering project

Run 64-bit Linux on LiteX + RocketChip

Build your hardware, easily!

low cost software radio platform

Python interface to FPGA interchange format

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA

PicoRV

EVEREST: e-Versatile Research Stick for peoples

micropython ESP32 programmer/flasher for ECP5 JTAG

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

Build Customized FPGA Implementations for Vivado

A padring generator for ASICs

IceCore Ice40 HX based modular core

Mutation Cover with Yosys (MCY)

SystemVerilog to Verilog conversion

Homebrew formulae for building FPGA bitstreams with open-source tools.

2 hour crash course in FPGAs

Small, but powerful FPGA development board based on the Lattice ECP5.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

妖刀夢渡

This project is no longer maintained Not recommended for product development.

Python to AXI4

Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.

Bitwise is an educational project where we create the software/hardware stack for a computer from scratch.

A PCB with SRAM, buttons, LEDs and some pmod-compatible connectors for the Lattice HX8K Breakout Board

❄️ Visual editor for open FPGA boards

nextpnr portable FPGA place and route tool