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Commits on Mar 2, 2024

• Merge remote-tracking branch 'upstream/master'

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Commits on Oct 18, 2023

• RISC-V Co Processor: Clear escape flag before (re)entering basic (#16)

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Commits on Sep 24, 2023

• RISC-V Co Processor: Update error handler for 32-bit error code

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• RISC-V Co Processor: Comments only

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Commits on Sep 22, 2023

• RISC-V Co Processor: Escape sometimes being reported when pressing RETURN (#15)

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Commits on Sep 16, 2023

• RISC-V Co Processor: Add x#<itemi> register name prefix (#12)

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Commits on Sep 14, 2023

• RISC-V Co Processor: Add some priviliged instructions to assembler (#11)

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• RISC-V Co Processor: Add ZICSR instructions to assembler (#8)

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• RISC-V Co Processor: Include Build info in startup banner (#10)

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Commits on Sep 11, 2023

• RISC-V Co Processor: Implement missing load global / store global pseudo instructions (#4)

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Commits on Sep 10, 2023

• RISC-V Co Processor: Sanitise LOAD/SAVE filenames (#5)

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• RISC-V Co Processor: Assembler now handles tokenized mnemonics (#7)

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• RISC-V Co Processor: EQUD no longer forces 4-byte alignment (#6)

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Commits on Sep 9, 2023

• RISC-V Co Processor: Update OS_HANDLERS parameters

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• RISC-V Co Processor: Set RVBASIC as current program so it survives soft break

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Commits on Sep 8, 2023

• RISC-V Co Processor: Change syscall base to 0xAC0000

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• RISC-V Co Processor: Use #defines for syscall numbers (nop)

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• RISC-V Co Processor: Update OSFILE and OSGBPB APIs to use individual registers (alpha2)

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Commits on Sep 7, 2023

• RISC-V Co Processor: Fix minor issue in LI that resulted in an unnecessary instruction for -2048 <= imm <= -1

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• RISC-V Co Processor: LI pseudo instruction less likey to vary between passes (fixed #1)

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• RISC-V Co Processor: LA pseudo instruction always emits two instructions (fixed #1)

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• RISC-V Co Processor: Simplified local * command parsing (fixes #3)

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• RISC-V Co Processor: Support Load/Store with immedate offset ommitted (fixes #2)

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• RISC-V Co Processor: Fix hopelessly broken AUIPC instruction

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Commits on Sep 1, 2023

• RISC-V Co Processor: Fix problem with AUTO and Escape

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Commits on Aug 20, 2023

• RISC-V Co Processor: Fix parsing error in branch instructions

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Commits on Aug 19, 2023

• RISC-V Co Processor: Fix edge case with 64-bit decimal print code

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Commits on Aug 18, 2023

• RISC-V Co Processor: Start address now F80000

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• RISC-V Co Processor: Use OSBYTE to determine user memory bounds

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• RISC-V Co Processor: Refactor _osbyte interface

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• RISC-V Co Processor: Seperate out low level MOS API from BBC Masic MOS API

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• RISC-V Co Processor: More work on wrapper

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• RISC-V Co Processor: Build .ssd disk image

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• RISC-V Co Processor: Fix *.

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• RISC-V Co Processor: Added CALL and TAIL pseudo instructions

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