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Modern IRC Client for the web, desktop and mobile.

TypeScript 157 15 Updated Feb 17, 2026

Bound Book Format: A high-performance container format for comics and manga

C 377 5 Updated Feb 7, 2026
Verilog 6 Updated Jan 18, 2026

Run your GitHub Actions locally 🚀

Go 68,827 1,850 Updated Feb 10, 2026

☕ GDBFrontend is an easy, flexible and extensible gui debugger.

JavaScript 3,004 112 Updated Nov 12, 2025

FM synth reverse-engineering

88 3 Updated Oct 1, 2023

Highly accurate Yamaha OPL3 (YMF262, CT1747) emulator

C 219 25 Updated Jul 1, 2024

Simulation model of the Atari STE GSTMCU

Verilog 11 1 Updated Jan 2, 2025

Optical character recognition for Japanese text, with the main focus being Japanese manga

Python 2,536 124 Updated Jun 14, 2025

GammaRay is a tool to poke around in a Qt-application and also to manipulate the application to some extent.

C++ 1,820 314 Updated Feb 13, 2026

ATARI-ST SNDH Archive music browser/player

C++ 52 5 Updated Sep 20, 2025

Activate any version of Windows and Office, forever

Dockerfile 2,163 189 Updated Oct 23, 2025

WurthElektronik_KiCad-Library

86 5 Updated Jan 29, 2026

draws an SVG schematic from a JSON netlist

JavaScript 764 103 Updated Jan 25, 2024

Stacker is a static analysis tool for analyzing the amount of stack space used by a program.

Python 11 2 Updated Jun 5, 2023

🚀 Level up your GitHub profile readme with customizable cards including LOC statistics!

Python 16,111 119 Updated Jan 25, 2025

Static analyzer for C/C++ based on the theory of Abstract Interpretation.

C++ 3,114 218 Updated Apr 24, 2025

WAL enables programmable waveform analysis.

Python 164 24 Updated Nov 10, 2025

An open-source remote desktop application designed for self-hosting, as an alternative to TeamViewer.

Rust 107,694 16,010 Updated Feb 17, 2026

Smol 2-stage RISC-V processor in nMigen

Python 26 2 Updated May 6, 2021

Minimal RV32I processor with register file in RAM

Verilog 4 1 Updated Sep 10, 2022

Example Hazard3 + OpenDAP RISC-V SWD SoC integration

Verilog 11 1 Updated Apr 20, 2023

5-stage RISC-V CPU, originally developed for RISCBoy

Verilog 35 1 Updated Jul 1, 2023

Carrier for Blackpill F411 when used as Blackmagic Probe

2 1 Updated Oct 3, 2024

3-stage RV32IMACZb* processor with debug

Verilog 1,004 79 Updated Dec 14, 2025

A flexible (literally) interface for connecting FPGA modules.

6 Updated May 27, 2024

Deeply Embeddable bare-metal C++ standard library

C++ 13 Updated Feb 16, 2025

Interactive C/C++ preprocessor macro debugger

C++ 180 9 Updated Dec 18, 2020

ensuring positive reinforcement during long, tiring code sessions~

Rust 123 1 Updated Feb 14, 2026
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