Implementation of a Tensor Processing Unit for embedded systems and the IoT.

JieLi SoC/MCU flasher & dumper (sorta)

JieLi SoC/MCU flasher & dumper (sorta)

珠海杰理AC632N系列芯片研究

Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra

6-stage dual-issue in-order superscalar risc-v cpu

The following repository consists of steps followed while doing the Advanced Physical Design Using OpenLANE/SKY130 workshop. The workshop focuses on the complete ASIC flow approach from RTL2GDS usi…

Minimal system project with riscv core picorv32 : asm startup + linker script + c example + verilog system + testbench + Makefile

National French competition for optimizing the power consumption of an Application class 6-stage RISC-V CPU (CORE-V CVA6)

Hardware Scheduled Dual Core RISC-V (OOO IMAC + Pipelined IA) Processor with a snoop bus interconnect (MESI Protocol) -- all in SystemVerilog

RTL modules development to expand a RISC-V RV32I core with the capabilities of the instructions sets M and F by student from the UAB, Spain.

ARCINO is a 32bit ultra low power core based on RISC-V RV 32IMC

This project is on a Dual core Lockstep Processor in RISC-V for functional safety .

System Verilog Implementation of a basic Risc-V core.

This Project implements a 5 stage pipelining RISCV processor using a single ported byte addressable memory for both data and instructions.

Pipeline core in RISC-V ISA with data forwarding.

Stage 2: Designed a custom RISC-V SOC-class multi-core CPU with lightweight snooping-based cache coherence and heterogeneous acceleration, integrating multiple CPU cores, vector extensions, scrat…

RISC-V M-Extension Coprocessor for PicoRV32 Core

ysyx project : risc-v 64 cpu core

A 5-stage pipelined single-core processor with support for M extension prefetching, and 2-level set-associative cache.

A 5 Day RISC-V MYTH WORKSHOP conducted by VLSIDesign and REDWOOD EDA to help students in developing their own RISC-V CPU Core

Extension to RISC-V ISA for an Application-Specific Resource-Scarce Soft-Core CNN Processor (2022)

Open-source RISC-V Cores

Homebrew Soft-Core RISC-V Processor

Verifying RISC-V core SERV

A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations

Core for QuantiumV - A RISC-V SoC collab work.

A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations

A curated list of spec, maturity comparison between current Open RISC-V cores.