Let z3_ir_translator handle zero-width DynamicBitSlice

PiperOrigin-RevId: 765364231

Refactor jit buffer handling.

This is a cleanup of buffer handling in the JIT. No functional change. Specific changes:

* Add a struct `TypeBufferMetadata` which holds all the metadata (size, alighment, etc) about a buffer which can hold a value of a particular XLS type in the JIT. Previously these fields were all passed around separately.

* Split `JitArgumentSet` into two different subclasses: a base version which does not own the allocation, and a derived version which does. This makes it easier to construct the argument set with aliased register buffers used in the block jit. These aliased buffers allow pingponging to avoid copying the register contents from cycle to cycle.

This change is in preparation for adding multi-write registers which can simplify aspects of codegen but require additional output buffers for the block jit.

PiperOrigin-RevId: 764984685

Integrate LLVM at llvm/llvm-project@2b8bff6f66fd

Updates LLVM usage to match
[2b8bff6f66fd](https://github.com/llvm/llvm-project/commit/2b8bff6f66fd)

PiperOrigin-RevId: 764439621

xls/fuzzer: add crasher_2025-05-25_eb23

See #2263

PiperOrigin-RevId: 763291196

In narrowing, include partial-information QE even when proc-state evo…

Make system verilog type a field on PortNode.

Previously, this value was carried along as bag-on-the-side metadata.

PiperOrigin-RevId: 762234853

[XLS] When comparing TreeBitLocations, compare node ID rather than po…

Speed up PipelineSchedule::FromProto.

It was previously quadratic in the number of nodes because looking up a node by name is slow.

PiperOrigin-RevId: 761213964

The tests for the resource sharing pass were rewritten to utilize the…

Automated Code Change

PiperOrigin-RevId: 760028989