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1. trial_task_1 trial_task_1 Public

   trial task

   C

2. trial_task_2 trial_task_2 Public

   trial task 2

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3. scr1 scr1 Public

   Forked from syntacore/scr1

   SCR1 is an open-source RISC-V compatible MCU core

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4. riscv-formal riscv-formal Public

   Forked from SymbioticEDA/riscv-formal

   RISC-V Formal Verification Framework

   Verilog

5. picorv32 picorv32 Public

   Forked from YosysHQ/picorv32

   PicoRV32 - A Size-Optimized RISC-V CPU

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6. riscv_fuzz riscv_fuzz Public

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