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VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug

TypeScript 36 Updated Nov 6, 2025

Show where time is wasted during the context upload of `docker build`

Go 346 17 Updated Apr 12, 2021

A low-level virtualization interface for Linux-based systems using WebAssembly

C 175 18 Updated Jan 20, 2026

Terraform module for scalable GitHub action runners on AWS

TypeScript 3,000 704 Updated Feb 16, 2026

Enable locally-located assets in Nuxt Content

TypeScript 124 13 Updated Feb 11, 2026

HIBA is a system built on top of regular OpenSSH certificate-based authentication that allows to manage flexible authorization of principals on pools of target hosts without the need to push custom…

C 390 17 Updated May 28, 2025

A language that compiles to Bash and Windows Batch

OCaml 4,338 168 Updated Apr 30, 2023

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,764 690 Updated Feb 16, 2026

OpenTitan: Open source silicon root of trust

SystemVerilog 3,139 957 Updated Feb 16, 2026

Scan, index, and archive all of your paper documents

Python 7,929 500 Updated Apr 6, 2021

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

C 88 25 Updated Mar 8, 2021