External Release v2026.05.19

This release aligns XED with Intel® ISE Revision 061 and Intel® AVX10.2 Revision 7.0.

---

- Dropped USER-MSR support from the Diamond Rapids and Nova Lake chips.
- Moved APX-promoted USER-MSR variants to the FUTURE XED chip and fixed their XED extension name.
- Updated `VCVTHF82PH` exception type.

- Switched the Windows XED example tool from static to dynamic `dbghelp.dll` loading, restricting resolution to trusted locations.
- Replaced the obsolete `--vc-dir` build knob with a working `--toolchain-vs` option for selecting a Visual Studio installation root directory.
- Expanded `xed_to_db.py` metadata export with structured CPUID records and list-valued `reg_required` data for ranged `REG` constraints, and added usage guidance to `pysrc/README.md`.

- Improved EVEX immediate sign-extension in the disassembler.

External Release v2026.03.18

This release aligns XED with Intel® AVX10.2 Revision 6.0 and Intel® APX Revision 8.0.

- Updated AVX10.2 FP16-FP8 conversion definitions to bypass MXCSR flag updates.
- Renamed the AVX10.2 CPUID bit `AVX10_VNNI_INT` to `AVX10_V1_AUX`.
- Updated the AVX10.2 `VCVT2PS2PHX` exception class.

- Expanded `xed_to_db.py` metadata export with integer-valued operand and element widths, element types, and `vsib` and `avx512_tuple` fields.
- Improved `dbghelp.dll` handling in XED example tool by using the Windows loader-selected DLL when version 6 or later is available.
  Added a `-no-dbghelp` option to disable symbol resolution at runtime.

- Fixed EVEX Disp8 scaling for instructions with sub-byte element sizes.
- Fixed `VEXTRACTF128` operand width.

External Release v2026.02.17

This release aligns XED with Intel® SDM Revision 090 and the latest Intel Software Security Guidance.

- Added support for the IBHF instruction.
- Dropped Lunar Lake (LNL) chip configuration (ISA alias of Arrow Lake).

- Introduced systematic API input validation across XED's APIs, with explicit precondition checks to improve robustness against invalid inputs and misuse.
   Users can disable API validation using the `--no-api-check` build knob.
- Extended `xed_assert()` coverage across internal APIs for improved diagnostics in assert builds.
- Updated build support for Clang 20.
- Enhanced `xed_to_db.py` with a version field in JSON output and data integrity validation for nested structures.
- Introduced APX encoder precondition handling for NF (No Flags) instructions, which now implicitly enforces EVEX encoding.

- Fixed the `--no-cet` build option.

External Release v2025.12.14

This release aligns XED with Intel ISE Revision 060 and adds support for the
Nova Lake (NVL) chip configuration.

---

- New instruction metadata export utility (`xed_to_db.py`):
  Introduced a user-facing utility that exposes XED instruction metadata through a
  type-safe Python dataclass for direct consumption in Python frameworks, and also
  supports exporting the same data as structured JSON files. This enables external
  tools to consume the instruction database either programmatically or via JSON,
  without parsing internal XED data files, and includes serialization and
  validation helpers.

- Fixed the `xed_decoded_inst_vector_length_bits()` API to consistently return a
  vector length of 128 bits for SIMD scalar instructions, where EVEX.VL is ignored.

- Removed the redundant `ptr` keyword from AMX instruction memory disassembly,
  since memory width is defined by `LDTILECFG`.

- Enhanced the XED examples README with detailed explanations and a standalone
  build guide.

- Improved Python code robustness and general maintainability.

External Release v2025.11.23

This release aligns XED with the latest Intel architecture specifications,
including:
- Intel SDM Revision 089
- Intel ISE Revision 059
- Intel APX Revision 7.0

---

Key ISA updates:
- Dropped support for AMX-TRANSPOSE instructions.
- Updated CPUID sensitivity for several APX instructions to include the
  APX_NCI_NDD_NF bit.
- Added support for the UDB undefined instruction.
- Updated the supported chip list for the PBNDKB instruction.

---

General improvements:
- Refactored XED extensions for APX-promoted instructions to align with
  legacy ISA extensions. This treats APX promotions as ISA optimizations
  rather than new extensions, improving XED classification.
- Added a new XED classifier for APX-F (Foundation) instructions.
  Note: The existing xed_classify_apx() API is unchanged and continues
  to detect instructions with APX-specific encodings.
- Renamed the RAO_INT XED extension to RAO.
- Enhanced the XED builder to include XedPy Python sources and examples
  when the --xedpy build knob is used.
- Improved pysrc/gen_cpuid.py output by supporting grouped CPUID information
  and filtering duplicate entries.
- Added extended documentation and a new README file for XED pysrc scripts.
- Improved builder error messaging by removing the "fatal" token from
  non-verbose builds that encounter a failed git describe, preventing
  confusion during build failures.
- Renamed the AMD/VIA-enabled build option to AMD/VIA.

---

Fixes:
- Added missing RING0 attributes for multiple instructions
  (Fixes #350).
- Dropped CLDEMOTE from ADL.
- Fixed the examples/mfile.py builder to support manual, direct execution
  inside the XED kit.
- Added missing XED APIs in the dynamic XED build (Fixes #353).
- Fixed XED examples Clang 19 build warnings (Fixes #354,
  closes #351).
- Improved ENC2 resilience with multiple internal stability enhancements
  (Fixes #355).
- Marked xed_decoded_inst_get_byte() as a private API, as it is not intended
  or safe for library consumers.
- Dropped a redundant XED_DLL_GLOBAL library C macro (Fixes #352).
- Fixed the XED library build when MPX support is excluded.

Co-authored-by: marjevan <marjevan@users.noreply.github.com>

External Release v2025.06.08

This release aligns XED with Intel’s latest architecture specifications, including:
- Intel® SDM Revision 087
- Intel® ISE Revision 057
- Intel® AVX10.2 Revision 5.0

Key ISA-related changes:
- Dropped support for AVX10/256-specific architectural features, including YMM embedded rounding and AVX10 VL-specific CPUID enumerations
- Updated CPUID sensitivity for various AVX10.2 instructions
- Updated exception class handling for several AVX512 instructions

---

- Modified arguments of the `xed_operand_print()` decoder API to correctly represent the destination EVEX operand (the old signature is deprecated and replaced)
- Restructured XED examples for improved clarity, naming, and usability
- Improved XedPy with more robust initialization and initial high-level Python encode APIs
- Migrated internal types to use `stdint.h` exclusively
- Added ENC2 support for REX2 prefix encoding with EGPR operands

---

- Fixed many build exclusion options; deprecated several build flavors in favor of `--no-avx512` as the minimal build kit (Fixes #336)
- Encoder: fixed AMX encoding for non-index SIBMEM operands
- Added missing and removed incorrect non-temporal memory hints
- Resolved Python 3.12 compatibility warnings (Closes #346)
- Fixed AMD `INVLPGB` operand specification (Closes #345)
- Corrected AMD `PREFETCH_EXCLUSIVE` mnemonic name (Fixes #215)
- Updated instruction definitions for various AVX512 instructions
- Applied various documentation improvements (Fixes #347)

Co-authored-by: marjevan <marjevan@users.noreply.github.com>

External Release v2025.03.02

The release updates XED according to Intel's latest ISA publications, including
AVX10.2 (Revision 3.0) and APX (Revision 6.0) architecture specifications.
This release also introduces major enhancements to the decoder control APIs.

ISA Updates
- Added new APX instructions that promote the Diamond Rapids ISA.
- Added support for AVX10.2 mnemonic renames.
- Improved definitions for Intel SDM-recommended multi-byte NOPs (See
  #340).
- Fixed ISA-SET discrepancy for FISTTP.
- Corrected element types for VCVTQQ2PD and VGET{MANT,EXP}PBF16 instructions.
- Refined TSX ISA definition for accurate disassembly representation.
- Dropped compatibility mode SYSCALL per Intel's latest FRED specification.
- Added missing `PROTECTED_MODE` and `NOP` XED attributes for existing ISA.

-----
General
- Python APIs: The `_py` binding APIs are now autogenerated during the build for
  an accurate representation of the chosen build kit. For more information, check
  the `xed\pyext\examples\README.md` file.
- Python APIs example: Enhancements for the CFFI example and XedPy class.
- Updated the XED build to support Clang versions 17 and 18.
- Improved XED examples documentation and source-code comments.
- Simplified the encode request for AVX10/256VL Embedded Rounding Control
  instructions by setting only the `ROUNDC` XED operand.

-----
Fixes
- Fixed UBSan errors (closes #339).
- Fixed Sierra-Forest and other chip-excluded builds using the `--no-{chip}` build
  knobs (fixes #343).
- Corrected SIB segment mapping for the R21 register (fixes #340).
- Internal improvements and code cleanup (fixes #340).

-----
Decoder
- Added REAL-mode legality checks (`INVALID_MODE` error for illegal instructions).
- Disassembler: Added support for Intel's recommended APX assembly syntax for NF
  (No Flags) and DFV (Default Flags Values) instructions.
- Enhanced APIs for APX/DFV instructions to ensure simplicity and efficiency. See
  the API reference page and the `xed-ex1.c` example for more details.

-----
API Improvements for Decoder ISA Control

The XED decoder control APIs now fully support the `xed_chip_features_t`
structure, offering greater flexibility and control compared to the
`xed_chip_enum_t` concept, enabling users to customize feature sets with
precision.
- Improved the `xed_chip_features_t` APIs to provide fine-grained control over
  ISA initialization. This approach is now recommended over the raw
  `xed3_operand_set_*` APIs.
- Introduced a new API, `xed_set_decoder_modes()`, which allows explicit
  initialization of decoder modes with improved performance through one-time
  decoder ISA initialization.

Backward Compatibility
- Backward compatibility for existing APIs is maintained.
- Backward compatibility for decoder initialization of several ISA features has
  been deprecated. Previously default-on features like `P4` (PAUSE), `LZCNT`
  (replacing BSR), and `TZCNT` (replacing BSF) are now disabled by default unless
  explicitly enabled by users through the raw XED setter APIs or the
  chip/chip-features APIs.

Decoder PREFETCH as NOP - New Capability
- Based on decoder ISA initialization, the XED decoder now returns NOPs instead
  of PREFETCH instructions when PREFETCH is not supported by the chip/features.
  Previously, PREFETCH instructions were returned as illegal if they were
  unsupported by the XED chip

Usage Example
- For detailed usage guidance, refer to the XED `xed-ex4.c` example tool, which
  includes decoder initialization recommendations for dual-encoding ISA.

Co-authored-by: marjevan <marjevan@users.noreply.github.com>

External Release v2024.11.04

The release updates XED according to Intel's latest ISA publications, as detailed in
ISE054, ISE055 and AVX10.2-rev2.0.

This version includes support for:
  - Intel Diamond Rapids (DMR) chip
  - Diamond Rapids AMX instructions
  - MOVRS and AVX10-MOVRS instructions
  - SM4 EVEX instructions
  - MSR-IMM instructions (including APX-promoted variants)
  - Encoding updates for various AVX10.2 instructions
  - Other updates across XED chip definitions

General
  - Shared Library Build for Python: Introduces a unique XED shared library build, exposing all XED APIs via a shared library object. This enables the library to be loaded in Python environments, allowing interaction with XED using Python APIs.
  See the [examples in pyext/README.md](pyext/examples/README.md) for more details. (Closes #302)
  - Disassembler Enhancements: Adds support for emitting CS/DS ignored branch hint prefixes, configurable through the `xed_format_options_t` structure.
  - Updates minimum Python requirement from 3.8 to 3.9.
  - Improves Internal ISA definition APX files (See #338)

Fixes
  - Resolves C11 build warnings with GCC (Fixes #332)
  - Improves length and error reporting for illegal instructions caused by a zeroed EVEX map (Resolves #334)

Co-authored-by: Arjevani, Maor <maor.arjevani@intel.com>

External Release v2024.09.09

General:
- Set the default security build level to 2, enabling the build of a more secure C library by default. If needed, users can lower the security level using the `--security-level=1` build option.

Add:
- Add AVX10/256 VL-ignored (Neither SAE nor Embedded-RC behavior) instructions.
- Add ENC2 support for AVX10/256VL Embedded-RC instructions.

Fix:
- Fix potential buffer overflow in ILD (resolves #331)
- Resolve Python 3.12 Regex syntax warnings.

Co-authored-by: marjevan <marjevan@users.noreply.github.com>

External Release v2024.08.15

The release adds support for Intel Advanced Vector Extensions 10.2 (Intel® AVX10.2) ISA,
compliant with the AVX10.2 architecture specification rev-1.0 (July 2024).

Added:
- Decoder and encoder support for Intel AVX10.2 new ISA (No ENC2 support for YMM embedded-RC)

Fixed:
- MPX: Removed wrong support for 16-bit addressing variants (#57)

Co-authored-by: marjevan <marjevan@users.noreply.github.com>