Turn any technical book PDF into a Claude Code skill — ready to study, reference, and use while you work.

AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short).

Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)

x64 semantics in Lean

RISC-V Logic Analyzer Trace Specification (Logic Analyzer Trace TG, RVS-4762)

xverif is a local toolkit for chip-verification debug agents. It contains deterministic tools for design and waveform debug, coverage, bit calculations, structured entry decoding, log source locati…

OpenROAD's Chatbot Assistant

Library of open source PDKs

PDK for 2nm Technology Node

This repository modifies the original riscv-formal framework to work with Synopsys VC Formal. It includes updates to scripts and configurations for formal verification of RISC-V cores, focusing sol…

This is an online course where you can learn and master the skill of low-level performance analysis and tuning.

A Modern SystemVerilog Coding IDE.

Awesome Artificial Intelligence for Electronic Design Automation Papers.

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

Deep learning toolkit-enabled VLSI placement

Lean math proofs generated by AlphaProof Nexus and accompanying natural language prose proofs.

AOCL-Utils library to get CPU architecture, Cache information and CPU features flags etc.

AI-native Chiplet design flow based on open-source EDA toolchain

GeST (Generating Stress-Tests) is a framework for automatic CPU stress-test generation using genetic algorithms. SAGA extends GeST with a surrogate model to reduce costly evaluations during test ge…

FIRESTARTER: A Processor Stress Test Utility. This repository contains the source code generator. Our releases (including the generated source code and precompiled binaries) are available at https:…

A digital circuit verification library for Lean4

A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.

FreeCAD MCP(Model Context Protocol) server

Vibe with Xiaomi AI Speaker

SV/DPI library allowing multiple simulations/platforms to run in parallel and communicate