Starred repositories
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
High level synthesis language for hardware design
Testing processors with Random Instruction Generation
A Pythonic implementation of SystemVerilog-style Interface, Modport, and Clocking Block for cocotb. Bridge the gap between hardware verification concepts and Python with race-free, timing-accurate …
Verilog engineers learning Haskell. Haskell engineers learning hardware. Everybody emerges with superpowers. No exceptions.
Boilerplate codebase for Embedded FPGA kernel development via YosysHQ & BSV
pyslang-mcp is a read-only Model Context Protocol server for compiler-backed Verilog and SystemVerilog analysis. It uses pyslang to parse HDL projects, report diagnostics, inspect design units and …
Independently maintained, community fork of Psiphon Android client
Receiving unencrypted data with MITM, Then send it with DomainFronting
Bluespec translator for surfer waveform viewer.
A Walkie-Talkie based around the ESP32 using UDP broadcast or ESP-NOW
Sign, notarize, and package macOS CLI tools and applications written in any language. Available as both a CLI and a Go library.
Sim provides a discrete event simulation engine, to facilitate Rust- and npm-based simulation products and projects
High-performance asynchronous computation framework for system simulation
A discrete-time events simulation framework, written in rust, using the generator experimental feature
DESRu is a library which contains the bare minimum components to write discrete event simulations.
Example of how to use UVM with Verilator
Chisel-only matrix multiplier for AMD/Xilinx Alveo boards
A Rust Embedded-HAL for the rp series microcontrollers
Raspberry Pi: development platform for PlatformIO
A Verilog implementation of a processor cache.
A machine learning accelerator core designed for energy-efficient AI at the edge.