Skip to content
View ldk999's full-sized avatar

Block or report ldk999

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

A machine learning accelerator core designed for energy-efficient AI at the edge.

Emacs Lisp 2,490 317 Updated Jul 31, 2026

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

Verilog 543 67 Updated Jul 18, 2025

The Ultra-Low Power RISC-V Core

Verilog 1,892 429 Updated Aug 6, 2025

this repository is vim cfg for verilog.

Vim Script 57 4 Updated Apr 24, 2026

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,641 363 Updated Jul 31, 2026
C++ 58 10 Updated Oct 14, 2025

3DIC system prediction platform

MATLAB 2 1 Updated Nov 19, 2018