Clip chaining for MiniMax H3 in ComfyUI - motion and audio genuinely continue across joins

[CSUR] A Survey on Video Diffusion Models

Detailed python notes & code for lectures and exercises of Andrej Karpathy's course "Neural Networks: Zero to Hero." The course is focused on building neural networks from scratch.

classic books of computer science!

Examples and guides for using the OpenAI API

SYCL Academy, a set of learning materials for SYCL heterogeneous programming

Source code for 'Data Parallel C++: Programming Accelerated Systems Using C++ and SYCL' by James Reinders, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, Xinmin Tian (Apress, 2023).

A simple profiler to count Nvidia PTX assembly instructions of OpenCL/SYCL/CUDA kernels for roofline model analysis.

official repository of "Revisiting Convolutional Sparse Coding for Image Denoising: From a Multi-scale Perspective"

a software library containing BLAS functions written in OpenCL

FB (Facebook) + GEMM (General Matrix-Matrix Multiplication) - https://code.fb.com/ml-applications/fbgemm/

CFA (Colour Filter Array) demosaicing algorithms for Python

https://www.youtube.com/playlist?list=PLHae9ggVvqPgyRQQOtENr6hK0m1UquGaG

Build your hardware, easily!

Example designs for FPGA Drive FMC

Sample UVM code for axi ram dut

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).

high level synthesis

Codes for PP4FPGAs labs

RISC-V Integration for PYNQ

计算机组成与设计 硬件/软件接口 第5版 ; Patterson, Hennessy: Computer Organization and Design:The Hardware/Software Interface,5th Edition.

Parallel Programming for FPGAs -- An open-source high-level synthesis book

This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

An implementation of DisplayPort protocol for FPGAs

A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard

A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard