What's Changed

• [circt-bmc] don't error when no assertions are given by @TaoBi22 in #9433
• [Synth] Extract delay-aware tree building into reusable utility, NFC by @uenoku in #9430
• [LLHD] Add support for IntegerType to SROA by @jmolloy in #9386
• [circt-synth] Add pre-synthesis optimization passes by @uenoku in #9428
• [ArcRuntime] Add runtime library implementation for arcilator by @fzi-hielscher in #9356
• [FIRRTL] Domain inference by @rwy7 in #9106
• [Arc][ArcToLLVM] Add RuntimeModelOp by @fzi-hielscher in #9435
• [Arc][ArcToLLVM] Add InsertRuntime pass by @fzi-hielscher in #9357
• [arcilator][ArcRuntime] Integrate ArcRuntime by @fzi-hielscher in #9358
• [Sim] Add dynamic string type and basic ops by @KavyaChopra04 in #9438
• [LLHD] Fix multiply-driven signals being hoisted incorrectly by @fabianschuiki in #9421
• [circt-bmc] Move no assertions check into VerifToSMT by @TaoBi22 in #9441
• [ESI][RpcClient] Prevent deadlock on disconnect by @mortbopet in #9440
• [ESI][Runtime] Add cycle count and frequency to SysInfo by @teqdruid in #9423
• [NFC][VerifToSMT] Clean up initial value checks by @TaoBi22 in #9445
• Bump LLVM to f091be6d53e447391ca23142cf9d49b2654116d7 by @jpienaar in #9443
• [FIRRTL][FlattenMemory] Change FlattenMemory to also convert base types to UInt by @fzi-hielscher in #9448
• [ImportVerilog] Don't wrap concurrent assertions in ProcedureOps by @TaoBi22 in #9451
• Cleanup to no longer use deprecated make_scope_exit by @nigham in #9432
• Reduce import test to avoid flagged cases by @jpienaar in #9450
• [HW] Verify inner symbols InnerSymbolTable ports. by @dtzSiFive in #9447
• [circt-test] Add dynamic progress display; various usability tweaks by @fabianschuiki in #9452
• [ImportLiberty] Add Liberty file parser for circt-translate by @uenoku in #9439
• [Sim] Rework constant folding of sim.fmt.* operations by @fzi-hielscher in #9455
• [PyCDE] Fix seq.compreg name handling after LLVM submodule bump by @teqdruid in #9457
• [ESI] Fix memory leak in wrap operation folders by @teqdruid in #9458
• [ESI] Allow snoop operations on channels without unwrap by @teqdruid in #9459
• [Doc] Fix missing line continuation character in CMake build example by @m2kar in #9461
• [FIRRTL] Support special format substitutions in Chisel verification intrinsics by @uenoku in #9460
• [Synth] Refactor CutRewritePattern to return area/delay from match() by @uenoku in #9434
• Ignore additional property ports on firrtl.simulation target modules by @trmckay in #9462
• [ESI][Runtime] Always link nanobind module to static stdc++ by @teqdruid in #9463
• [FIRRTL][InferResets] Fix reset domain inference for multiple top-level modules by @uenoku in #9464
• [Comb] Replace BoolArrayAttr with DenseBoolArrayAttr in TruthTableOp by @uenoku in #9465
• [FIRRTL] Extend LinkCircuits to handle extmodule collisions by @unlsycn in #9404
• [Arc] Add nascent support for sim.proc.print and sim.fmt.* by @jmolloy in #9442
• [verif] Add combine-assert-like pass by @dobios in #9437
• [LTLToCore] Add core lowering for boolean implication by @TaoBi22 in #9456
• [LTLToCore] Add not, and, or lowerings by @TaoBi22 in #9478
• [cmake] consistently use includedir dest var for headers by @dtzSiFive in #9475
• [MooreToCore][Sim] added int-to-string support by @KavyaChopra04 in #9473
• [ImportLiberty] Treat space as logical AND in expression parser by @uenoku in #9470
• [FIRRTL] Drop domain associations w/ zero-width by @seldridge in #9477
• [FIRRTL] Same defname ExtModules in LowerClasses by @seldridge in #9472
• [Arc][Python] Add Arc dialect type property getters to Python bindings by @yassinz in #9484
• [circt-bmc] Add CombineAssertLike to pipeline by @TaoBi22 in #9479
• [ArcRuntime] Minor fixes and tweaks to ArcRuntime headers by @fzi-hielscher in #9486
• Add circt-tblgen, generate FIRRTL intrinsics docs by @fabianschuiki in #9454
• [VerifToSMT] Consider assertions inside funcs by @TaoBi22 in #9487
• [FIRRTL] Add folders for IntegerShrOp by @stomfaig in #9401
• [MooreToCore][Moore][ImportVerilog] Add basic ops for dynamic string type by @KavyaChopra04 in #9480
• [SV] Add InnerRefUserOpInterface to sv.verbatim by @uenoku in #9492
• [Support] [Synth] Rename NPNClass to TruthTable and add cofactor utilities by @uenoku in #9493
• Update .clang-format to disable TableGen by @uenoku in #9499
• [ImportVerilog] Add support for parameter-typed class member access by @Scheremo in #9500
• [circt-bmc] add hw-flatten-modules to pipeline by @TaoBi22 in #9495
• [hw-flatten-modules] Add option to inline public modules by @TaoBi22 in #9501
• [circt-bmc] Allow public module inlining by @TaoBi22 in #9502
• [Arc] Add onInitialized runtime hook by @fzi-hielscher in #9497
• [Arc] Add TraceTap attribute and annotate StateWriteOps of named states by @fzi-hielscher in #9498
• Add attribute to track external requirements for external and verbatim modules by @trmckay in #9496
• [Support] Add ISOP extraction utilities to TruthTable by @uenoku in #9506
• [ImportVerilog] Fix class method prototype resolution by @Scheremo in #9508
• [ImportVerilog] Implement support for null literals by @Scheremo in #9509
• [circt-opt] Add pass --convert-core-to-fsm by @AtticusKuhn in #8852
• [CoreToFSM] Cleanup non-deterministic iteration by @TaoBi22 in #9513
• [NFC][CoreToFSM] Drop unused variables by @TaoBi22 in #9514
• [CoreToFSM] Swap to Op::create by @TaoBi22 in #9515
• [CoreToFSM] Don't discard pattern driver result by @TaoBi22 in #9518
• [ImportVerilog] Add support for static class members by @Scheremo in #9517
• [py] Enable using default context in StructType.get by @jpienaar in #9512
• [Arc] Stabilize order in ModelInfoAnalysis, NFC by @fzi-hielscher in #9522
• [Synth] Add SOP balancing pass for delay optimization by @uenoku in #9511
• [LTL] Make PastOp return an i1 by @TaoBi22 in #9525
• [ImportVerilog] Add support for queue size() builtin by @Scheremo in #9524
• [ImportVerilog] add handle comparison ops and lower ==/!=/===/!== by @Scheremo in #9520
• [ImportVerilog] Allow static member hoisting from outside class by @Scheremo in #9521
• [ImportVerilog] Use comb.xor instead of ltl.not in $rose lowering by @TaoBi22 in #9526
• [FIRRTL][OM] Add, evaluate UnknownValueOp by @seldridge in #9474
• [FIRRTL] AnnotateInputOnlyModules: Skip modules with enabled layers by @uenoku in #9485
• [ImportVerilog] Fix class conversion crashes by @Scheremo in #9527
• [Arc] Add trace encoding infrastructure to ArcRuntime by @fzi-hielscher in #9503
• [Arc] Implement VCD trace encoder for ArcRuntime by @fzi-hielscher in #9504
• [LTL] Allow PastOp to take integer inputs by @TaoBi22 in #9532
• [ImportVerilog] Add support for unary $past builtin by @TaoBi22 in #9531
• [Synth][LongestPathAnalysis] Fix an incorrect instanch path by @uenoku in #9536
• [Arc] Add trace instrumentation to arcilator pipeline by @fzi-hielscher in #9505
• [Moore] Add ToBuiltinIntOp by @TaoBi22 in #9533
• ...

What's Changed

• [FIRRTL][GrandCentral] Add -no-views option. by @dtzSiFive in #9304
• [FIRRTL] Remove -allow-adding-ports-on-public-modules. by @dtzSiFive in #9301
• [verif] Add canonicalizers of clocked assertlikes by @seldridge in #9307
• [ESI] Include more WindowType info in manifest by @teqdruid in #9308
• Bump LLVM by @uenoku in #9306
• [FIRRTL] Use type inference for domain anon op by @rwy7 in #9312
• Document Copilot build setup (incl. PyCDE/ESI) and align integration image defaults by @Copilot in #9314
• [HW] Extend ElementType parsing to support union types by @yassinz in #9318
• [ESI][Runtime] Add non-list Window type read translations by @teqdruid in #9319
• [ESI][Runtime] Add non-list Window type write translations by @teqdruid in #9324
• [FIRRTL] Allow domain ports after associations by @seldridge in #9323
• [Verif] Add hw.constant Verif canonicalizers by @seldridge in #9325
• [ExportVerilog] Move declarations to the top of blocks when disallowDeclAssignments is set. by @uenoku in #9309
• [FIRRTL] Remove nonlocal field from annotations when NLA becomes local by @uenoku in #9329
• [ESI][Runtime] Translate message performance enhancements by @teqdruid in #9330
• [ESI][Runtime] Port Python bindings from pybind11 to nanobind by @Copilot in #9322
• [Python][LLVM] Add LLVM dialect and modify export llvm ir test by @yassinz in #9316
• [FIRRTL] Don't create empty modules in LowerLayers by @seldridge in #9333
• [FIRRTL] Fix Dedup issue caused by name shadowing by @fabianschuiki in #9336
• [ESI][Runtime] Parallel encoded list translation support by @teqdruid in #9334
• [FIRRTL][Dedup] Improve error messages for nested bundle type mismatches by @uenoku in #9338
• [FIRRTL][firtool] Add --inline-input-only-modules option to firtool by @uenoku in #9332
• [ESI] Improve RpcServer/CosimBackend usability through distributed package by @mortbopet in #9339
• [ImportVerilog][MooreToCore] Added support for int_to_real by @KavyaChopra04 in #9317
• [Sim][MooreToCore] Added octal formatting specifier for printing integers by @KavyaChopra04 in #9343
• Reapply "[circt-lsp-server] Make time source injectable" by @uenoku in #9342
• [Python][Sim] Bind sim dialect to python by @teqdruid in #9345
• [MooreToCore] Added real_to_int support by @KavyaChopra04 in #9346
• [LLHD] Fix HoistSignals with non-uniform drive delays by @fabianschuiki in #9349
• [ImportVerilog] Fix class property segfault and emit error by @fabianschuiki in #9347
• [Datapath] Convert comparison operators to arithmetic - avoiding multiple carry propagate adders by @cowardsa in #9344
• [PyCDE] Emit $info messages by @teqdruid in #9351
• [ESI] Factor out gRPC/proto usage in Cosim backend by @mortbopet in #9350
• [MooreToCore] Support float comparison operations by @maerhart in #9355
• [Arc] Use explicit CompReg reset instead of mux by @TaoBi22 in #9359
• [RTG] Add virtual register reduction pattern by @maerhart in #9283
• [ImportVerilog][Moore] Use more specific casting operations for string, real, and time casts by @maerhart in #9352
• [arcilator] add option to treat async firreg resets as sync by @TaoBi22 in #9360
• [MooreToCore] Support binary real operations by @maerhart in #9362
• [ESI][RpcClient] Implement synchronization for RPC completion by @mortbopet in #9363
• [ImportVerilog] Convert realtime values to f64 before operations by @maerhart in #9364
• [ImportVerilog] Properly cast subroutine call result value by @maerhart in #9365
• [ImportVerilog] Cast func call arguments to types matching func decl by @maerhart in #9366
• [ImportVerilog] Add support for program definitions by @fabianschuiki in #9377
• [MooreToCore] Lower $time to new LLHD current time op by @fabianschuiki in #9378
• [Seq] Update HWMemSimImpl's replSeqMem to support higher latency. by @mikeurbach in #9383
• [CombToArith] Don't reject unknown ops by @pscabot in #9394
• [Docs] Add tools page to the website and circt-verilog docs by @cowardsa in #9385
• [Transforms][MapArithToComb] Added best-effort lowering for Arith to Comb by @KavyaChopra04 in #9380
• [Arc][SplitFuncs] Ignore extern func ops by @TaoBi22 in #9393
• [ImportVerilog] Add basic event type support by @fabianschuiki in #9381
• [ArithToComb] Avoid converting float constants to HW by @fabianschuiki in #9407
• [FSMToCore] Add FSMToCore pass by @TaoBi22 in #9354
• [ImportVerilog] Replace FormatTimeOp with FormatIntOp by @fabianschuiki in #9406
• [LLHD] Add conversion ops between time and integer values by @fabianschuiki in #9405
• [Sim][MooreToCore] Added width, alignment and padding support for moore.fmt.int by @KavyaChopra04 in #9390
• [Python] Build and upload Python 3.14 wheel. by @richardxia in #9399
• [HWToLLVM] Ignore operations of other dialects by @fzi-hielscher in #9412
• [circt-test] Add options to pick only formal/simulation tests by @fabianschuiki in #9411
• [circt-test] Add supported test kind to runner config by @fabianschuiki in #9410
• [ESI] Handle possible exception in RpcServer::SendToServer by @mortbopet in #9409
• [MooreToCore][Sim] Added support for moore.fmt.real by @KavyaChopra04 in #9397
• Fix isSeqMem() check to allow externalization of memories with read-/write-latency >= 1 by @trmckay in #9419
• [LLHD] Processes with timed waits are not combinational by @fabianschuiki in #9422
• [circt-test] Install test runners alongside circt-test by @fabianschuiki in #9413
• [circt-test] Add Verilator test runner by @fabianschuiki in #9414
• [HW] Add pass to convert bitcast operations by @fzi-hielscher in #9425
• [arcilator][HWToLLVM] Use HWConvertBitcasts pass in arcilator pipeline by @fzi-hielscher in #9426
• [CI] Set timeout to individual lit tests by @uenoku in #9424
• [circt-test] Reuse firtool pipeline to emit split verilog by @fabianschuiki in #9427
• [CombToLLVM] Add conversion for comb::ReverseOp to LLVM dialect by @yassinz in #9431

New Contributors

• @KavyaChopra04 made their first contribution in #9317
• @pscabot made their first contribution in #9394

Full Changelog: firtool-1.138.0...firtool-1.139.0

What's Changed

• Bump LLVM by @7FM in #9235
• [Comb] Canonicalize power-of-two unsigned div/mod. by @uenoku in #9177
• [Datapath] Prevent FoldAddIntoCompress from introducing datapath ops from pure comb ops by @uenoku in #9178
• [PyCDE] Add support for union types by @teqdruid in #9242
• [ESI] Window lowered type fix by @teqdruid in #9243
• [PyCDE] Add support for ESI Windows by @teqdruid in #9244
• [PyCDE] Add Window.default_of to simplify window creation by @teqdruid in #9248
• [HWToLLVM][ArcToLLVM] Spill array values early by @fzi-hielscher in #9218
• [NFC][Docs] Add slang flag to getting started notes by @dobios in #9249
• [OM] Add UnknownValue to Evaluator by @seldridge in #9247
• [domaintool] Add -assign u support by @seldridge in #9251
• [Synth] Fix dependency in CMakeLists by @pineapplehunter in #9254
• [HWToBTOR2] Ignore printf related operations by @dobios in #9250
• [FIRRTL] Added getExtModuleName to FExtModuleOp to get the appropriate module name by @MrRoy09 in #9233
• [Arc][Python] Add Arc API bindings and dialect support by @yassinz in #9255
• [ci] Change static build to use Rocky Linux 8 by @seldridge in #9259
• [MooreToCore] Fix lowering of dynamic extracts of nested arrays by @fzi-hielscher in #9257
• [Synth] Add an API to get value for Object by @uenoku in #9261
• [Tests][Arcilator] Move arcilator JIT tests to integration tests by @fzi-hielscher in #9265
• [Comb] Add AssumeTwoValued pass by @TaoBi22 in #9264
• [Docs][NFC] Drop outdated hw comparison by @TaoBi22 in #9270
• [SwitchToIf] support multi-result scf.index_switch + add regression test by @Bynaryman in #9245
• [Comb] Add Truth Table Simplification Pass by @MrRoy09 in #9271
• [CombFolds] Fix crash in folding with non-integer attribute operands by @uenoku in #9273
• [NFC][Docs] Update README.md with enhanced build instructions for CIRCT by @doofin in #9203
• [HW] Add pass to parameterize constant ports on private modules. by @uenoku in #9266
• [circt-test] Add simulation test discovery by @fabianschuiki in #9279
• [Transform] Add convert-index-to-uint transform to normalize index compares before comb mapping by @Bynaryman in #9263
• [HW] Enhance FlattenModules pass with configurable inlining heuristics by @prithayan in #9224
• [circt-reduce] Support dialect plugins by @maerhart in #9282
• [FIRRTL] Fix crash in getPort(size_t) when missing inner symbols. by @dtzSiFive in #9284
• FileCheck linting: fix directive typos in tests by @dtzSiFive in #9286
• [HW][NFC] Add BitWidthTypeInterface for extensible bit width calculations by @Copilot in #9272
• [ESI] Add getBitWidth to ESI types by @teqdruid in #9289
• [ESI][LowerTypes] Add support for lowering embedded windows by @teqdruid in #9290
• [CI] Disable flaky Verilog LSP tests on macOS by @fabianschuiki in #9293
• [ESI][Runtime] Basic Window and List support by @teqdruid in #9267
• [Python] Add Pipeline dialect to Python bindings by @yassinz in #9276
• [Python] Add LLVM IR export support to Python bindings by @yassinz in #9275
• [ExportVerilog] Add disallowDeclAssignments lowering option. by @uenoku in #9298
• [Verif] Lower simulation tests to HW modules by @fabianschuiki in #9294
• [circt-synth] Disable test if yosys-abc unavailable by @fabianschuiki in #9295
• [LTL] Add Boolean Constant Op, use in Implication Canonicalizer by @seldridge in #9280
• [Comb] Add ConcatOp custom assembly format to enable nullaries by @TaoBi22 in #9274
• [ESI][Data windows] Add bulk transfer encoding by @teqdruid in #9299
• [OM] Remove Pure from ObjectOp to preserve identity by @fabianschuiki in #9303
• [Verif] Add more AssertLike canonicalizers by @seldridge in #9281
• [HW][Comb][ESI] Create a common function for HW constant materialization and add null check by @uenoku in #9300
• [FIRRTL] Add anonymous domain create op by @seldridge in #9296
• [HW] Add HWBypassInnerSymbols pass by @uenoku in #9291
• Per-module GrandCentral files when no bind file is specified by @trmckay in #9305

New Contributors

• @pineapplehunter made their first contribution in #9254
• @MrRoy09 made their first contribution in #9233
• @Bynaryman made their first contribution in #9245
• @doofin made their first contribution in #9203
• @Copilot made their first contribution in #9272
• @trmckay made their first contribution in #9305

Full Changelog: firtool-1.137.0...firtool-1.138.0

What's Changed

• Bump LLVM by @uenoku in #9170
• [MooreToCore] [1/4] Implement ClassDeclOp -> LLVMStructType conversion by @Scheremo in #9150
• [ImportVerilog] Also ignore TypeParameterSymbol in ClassDecl by @Scheremo in #9167
• [DatapathToComb] Simplify AND Array Lowering by @cowardsa in #9160
• [MooreToCore] [2/4] Add support to lower ClassNewOp to llvm.malloc by @Scheremo in #9151
• [MooreToCore] [3/4] Add support for lowering moore.class.upcast by @Scheremo in #9152
• [MooreToCore] [4/4] Add support for class.property_ref by @Scheremo in #9153
• [HWToLLVM] Do not take illegal shortcut in array_get lowering. by @fzi-hielscher in #9172
• [Arcilator] Print full values rather than truncating them. by @SimonEbner in #9120
• [ArcIntegrationTests] Match only full output lines, NFC by @fzi-hielscher in #9174
• [RTG][Elaboration] Fix incorrect set equality by @maerhart in #9175
• [FIRRTL] Support domain.define in LowerDomains by @seldridge in #9108
• [ImportVerilog] Add global variable support by @fabianschuiki in #9176
• [HWToBTOR2] Support unary case of variadics by @TaoBi22 in #9169
• [Conversion] Add comprehensive CombToLLVM conversion pass with func.func-only scope by @prithayan in #9105
• [ImportVerilog] Fix LValue generation for ClassPropertySymbol by @Scheremo in #9182
• [ImportVerilog] Enforce base class elaboration by @Scheremo in #9181
• [HWToBTOR2] Support variadic concat ops by @TaoBi22 in #9184
• [ESI] Telemetry implementation exposing metrics over MMIO by @teqdruid in #9185
• [RTG] Add ConstraintOp by @maerhart in #9186
• [RTG] Add alloc side-effect to virtual_reg, memory_block_declare, and memory_alloc by @maerhart in #9187
• [RTG] Folders for label decl ops by @maerhart in #9188
• [RTG] Add SetAttr and TupleAttr by @maerhart in #9189
• [FIRRTL] XorRCat canonicalizer: return success when successful by @maerhart in #9192
• [Arc][LLHD] Notify rewriter when modified-in-place in canonicalizers by @maerhart in #9193
• [HWToBTOR2] Add support for comb.replicate by @TaoBi22 in #9196
• [FIRRTL] Add domain support to instance choice by @rwy7 in #9197
• [FIRRTL] Add domain verification to instance-like ops by @rwy7 in #9074
• Add sv.module.verbatim op and use for firrtl.extmodule with BlackBoxInlineAnno/BlackBoxPathAnno by @tmckay-sifive in #9131
• [Moore][ImportVerilog] Implement support for virtual functions by @Scheremo in #9180
• Bump LLVM by @jpienaar in #9194
• [ESI][BSP] Introduce a pipelined channel demux and use it by @teqdruid in #9202
• [ImportVerilog][Moore] Add toupper and tolower string builtins by @TaoBi22 in #9200
• [circt-bmc][circt-lec] Add missing headers by @uenoku in #9201
• [RTG] Remove fixed_reg operation by @maerhart in #9204
• [HWToSMT] Add forsmt-lib-export flag by @TaoBi22 in #9198
• [MooreToCore] Error out on conversions to unsupported types by @TaoBi22 in #9199
• Fix inout port lowering for sv.verbatim.module by @tmckay-sifive in #9209
• [Verif] Always add clock trigger to HasBeenReset process by @fabianschuiki in #9212
• [Moore][ImportVerilog] Add SystemVerilog string.getc builtin by @TaoBi22 in #9220
• Revert addition of sv.verbatim.module by @tmckay-sifive in #9223
• [RTG] Add ImplicitConstraintOpInterface by @maerhart in #9205
• [arcilator] Add ability to specify args from CLI by @jpienaar in #9225
• [Arcilator] Timing scopes for JIT by @SimonEbner in #9210
• [Arcilator] Move pipeline into separate library. by @SimonEbner in #9213
• [ESI] Update esitester by @teqdruid in #9226
• [circt-verilog] Move pipeline into ImportVerilog. by @SimonEbner in #9208
• [ESI] List support in data windows by @teqdruid in #9228
• [ESI][Python] Plumb through windows types to Python by @teqdruid in #9231
• [ESI] Improve error message on type registry aliasing by @mortbopet in #9229
• [PyCDE] Removing pycde.types.types functionality by @teqdruid in #9237
• [Python] Add support for UnionType by @teqdruid in #9236
• [Moore][ImportVerilog] Add VTableOps and CreateVTables pass by @Scheremo in #9221
• [ESI][Runtime] Fixing service uniquifaction by @teqdruid in #9239
• [ESI][Runtime] Add JSON output for esiquery telemetry by @teqdruid in #9240
• Add sv.verbatim.source and sv.verbatim.module ops for inline black box extmodules by @tmckay-sifive in #9227
• [HWLegalizeModules] transform mux of array to muxes of elements by @ollef in #9230

Full Changelog: firtool-1.136.0...firtool-1.137.0

What's Changed

• [LLHD] Allow multiple layers of inlined functions to be followed by the same op by @georgerennie in #9119
• [Comb] Integer Overflow Analysis by @cowardsa in #9130
• [FIRRTL] Various reduction pattern tweaks by @fabianschuiki in #9132
• [Moore] [1/4] Implement ClassHandleType, ClassDeclarationOp by @Scheremo in #9133
• [Moore] [2/4] Implement new operator by @Scheremo in #9134
• Move to OpTy::create, OpBuilder::create is deprecated. by @dtzSiFive in #9142
• [ImportVerilog] Use initializer list for Cases, fix deprecation. by @dtzSiFive in #9143
• [Moore] [3/4] Implement class member access, upcast by @Scheremo in #9135
• [MooreToCore] Create implicit zero value for real variables by @fabianschuiki in #9147
• [Comb] Fix another recursive mux canonicalizer by @TaoBi22 in #9144
• [circt-bmc] add verif.formal support by @TaoBi22 in #9145
• [FIRRTL] Remove dead annotations relating to taps and blackboxes. by @dtzSiFive in #9146
• [FIRRTL] Remove GC DataTaps, unused upstream. by @dtzSiFive in #9149
• [Moore] Make names of constant ops more uniform by @fabianschuiki in #9148
• [Moore] [4/4] Implement direct class method calls by @Scheremo in #9136
• [FIRRTL] Remove internalPaths from IR. Drop ref statements. by @dtzSiFive in #9154
• Reland "[Moore] Implement direct class method calls" by @Scheremo in #9156
• [ImportVerilog] Fix capture callback chaining by @Scheremo in #9165
• [Bug][ImportVerilog] [1/2] Add support for class method forward decls by @Scheremo in #9158
• [ImportVerilog] [2/2] Add support to materialize ctor call on new call by @Scheremo in #9159
• [ImportVerilog] Add support for specialized parametric classes by @Scheremo in #9161
• [ImportVerilog][Moore] Add len string builtin by @TaoBi22 in #9163
• [HWToSMT] Add option to assert equalities over module outputs by @TaoBi22 in #9162
• [HWToBTOR2] Add support for (most) variadic ops by @TaoBi22 in #9155
• [NFC] Change name in BTOR2 test by @TaoBi22 in #9168

New Contributors

• @georgerennie made their first contribution in #9119

Full Changelog: firtool-1.135.0...firtool-1.136.0

What's Changed

• [FIRRTL] Add support for domain-connect driving instance-choice ports by @rwy7 in #9116
• [ImportVerilog] Add variableAssignCallback, allow LHS capture by @Scheremo in #9109
• [ImportVerilog] [2/2] Add post-pass to rewrite recursive call sites by @Scheremo in #9111
• [ImportVerilog] Harden SVReal materialization by @Scheremo in #9113
• [FIRRTL] getPortNameStr to getPortName, getPortName to getPortNameAttr by @rwy7 in #9117
• [ImportVerilog] Fix dynamic part-select index typing and add test by @Scheremo in #9114
• [Synth][LowerVariadic] Fix a dialect dependency by @uenoku in #9118
• [ImportVerilog] Add support for string materialization by @Scheremo in #9112
• [FIRRTL] Add more port-related functionality to instance ops by @rwy7 in #9125
• [FIRRTL] Make containingModule compatible with Chisel changes by @fabianschuiki in #9126
• [ImportVerilog] Support real-to-integer conversion in format string by @Scheremo in #9123
• [Moore][ImportVerilog] Add real-valued ops + real-aware import; refactor logical handling by @Scheremo in #9122
• [ESI] Add bitvector and arbitrary-width integer classes by @mortbopet in #9129
• Bump LLVM by @uenoku in #9121
• [Synth] Refactor and expose dropNonCriticalPaths to Python bindings by @uenoku in #9141
• [Python] Add regression check for OpOperand owner having wrong type by @fabianschuiki in #9139

Full Changelog: firtool-1.134.0...firtool-1.135.0

What's Changed

• [circt-verilog-lsp] Move to Slang's src mngr, drop LLVM src mngr by @Scheremo in #9045
• [circt-verilog-lsp][NFC] Break out implementation classes by @Scheremo in #9051
• [circt-verilog-lsp] Avoid recursing into other buffers when indexing by @Scheremo in #9055
• [RTG] Implement getAsmResultNames for FixedRegisterOp by @maerhart in #9058
• [CombToDatapath] Lower comb::SubOp by @uenoku in #9053
• [circt-synth] Allow AIGER file to be an input file by @uenoku in #9054
• [ESI] ChannelMMIO: decrease MMIO space per client by @teqdruid in #9062
• [RTG][EmbedValidationValuesPass] Allow ID duplicates if values match by @maerhart in #9061
• [RTG] Add isa.space operation by @maerhart in #9060
• [circt-verilog-lsp] Refactor VerilogIndex, add Package indexing by @Scheremo in #9065
• [CombToSynth] Compute Kogge-Stone prefix tree lazily in unsigned comparison lowering by @uenoku in #9050
• [ESI] Various tweaks to cosim scripts by @mortbopet in #9064
• [ESI][Runtime] Search for backends via env var by @teqdruid in #9070
• [RTG] Add VirtualRegisterConfigAttr by @maerhart in #9059
• [Comb] Fix mux canonicalizers for non-signless-ints by @teqdruid in #9071
• [circt-verilog-lsp] Minimize project-scope File IO by @Scheremo in #9056
• [circt-lsp-verilog] "Debounce" onDidChange calls; update in worker by @Scheremo in #9046
• [circt-lsp-server] Only enable unit tests if feature is enabled by @rwy7 in #9072
• [python][Synth] Provide fine-grained APIs for path queries by @uenoku in #9068
• [ImportVerilog][MooreToCore] Implement CHandle import and lowering by @Scheremo in #9077
• [ImportVerilog][MooreToCore] Re-land Implement CHandle import and low… by @Scheremo in #9079
• [FIRRTL] Add LowerDomains pass by @seldridge in #8929
• [MooreToCore] Support slicing of nested arrays by @SimonEbner in #9073
• [LLHD] Remove unused passes and unused memory types and ops by @fabianschuiki in #9078
• [circt-verilog-lsp-server] Simplify MaxCapForcesFlushDuringContinuousTyping by removing bakground thread by @uenoku in #9080
• [LLHD] Add new RefType to replace hw::InOutType by @fabianschuiki in #9081
• Fix minor typos by @SimonEbner in #9084
• [circt-lsp-server] Make time source injectable by @Scheremo in #9082
• [ImportVerilog] Add delayed assignment support by @fabianschuiki in #9085
• Revert "[circt-lsp-server] Make time source injectable" by @Scheremo in #9089
• [ImportVerilog][Moore] Add real-to-int & int-to-real operators by @Scheremo in #9088
• [FIRRTL] Add fields to domains by @seldridge in #9087
• [Synth] Enhance LowerVariadic pass with timing-aware optimization by @uenoku in #9086
• [Synth] Add MaximumAndCover Pass by @uenoku in #9090
• [ImportVerilog] Generalize materialization of constant real values by @Scheremo in #9092
• Bump LLVM to 3c53adec68b3e7be3d69bc4e24168e530097fce0. by @mikeurbach in #9063
• [FIRRTL] Add DomainDefineOp by @rwy7 in #9067
• [FIRRTL] DomainFieldAttr types are PropertyTypes by @seldridge in #9094
• Bump Slang to v9.1 by @fabianschuiki in #9097
• [FIRRTL] Update port insertion/erasure API for instance/instance-choice ops by @rwy7 in #9093
• [Synth][LowerVariaidc] Fix topological ordering and a pass phase ordering by @uenoku in #9095
• [ESI] Add opt-out of reversal in array C++ ser/de by @mortbopet in #9096
• [FIRRTL] Add LowerDomains to firtool pipeline by @seldridge in #9099
• [MooreToCore] Lower moore.real_constant to arith.constant by @Scheremo in #9100
• [FIRRTL] Fix dedup looking up wrong op in inner ref target check by @fabianschuiki in #9104
• [ImportVerilog] Allow functions to capture values from parent scope by @Scheremo in #9107
• [Synth] Fix race condition and memory corruption in longest path analysis caching by @uenoku in #9098

New Contributors

• @SimonEbner made their first contribution in #9073

Full Changelog: firtool-1.133.0...firtool-1.134.0

What's Changed

• [ESI][Cosim][Verilator] Switch to FST and dump time by @teqdruid in #9031
• Add a diagnostic for unsupported system calls with more than 1 argument by @likeamahoney in #9014
• [circt-verilog-lsp] Add support for -C command files for Slang, project-wide defintion lookup by @Scheremo in #9003
• [comb-to-synth] Implement Sklanskey Tree and Architecture Selection based on Attribute by @cowardsa in #9021
• fix: prevent canonicalize looping for extremely long time by @tianrui-wei in #9030
• [ESI][Cosim] Always use posix paths for questa by @mortbopet in #9035
• [ESI][Cosim] Add windows-equivalent for os.setsid by @mortbopet in #9034
• [ci] Set individual integration test timeout to 2m by @seldridge in #9039
• [ESI] Install CosimBackend.dll dependencies on windows by @mortbopet in #9037
• [FIRRTL] Update more symbol-sensitive ops after dedup by @fabianschuiki in #9016
• [ESI][Cosim] Switch to GUI mode via environment variable by @teqdruid in #9041
• [ESI][Cosim] Enable SAVE_WAVE functionality in SV driver by @teqdruid in #9042
• fix: guard eaglerinliner with detecting a valid circuit by @tianrui-wei in #9025
• [Datapath] Add initial delay optimisation pass by @cowardsa in #9038
• [SV] Support expressions as case patterns by @chiahsuantw in #9018
• [FIRRTL] Gate class deduplication behind an option by @fabianschuiki in #9040
• [CombToSynth] Use parallel-prefix tree for unsigned comparisons by @uenoku in #9048
• [Comb][circt-synth] Implement BalanceMux pass for optimizing mux chains by @uenoku in #9044

New Contributors

• @tianrui-wei made their first contribution in #9030

Full Changelog: firtool-1.132.0...firtool-1.133.0

What's Changed

• [ConvertToArcs] Allow ops with regions by @fabianschuiki in #8935
• [Synth][AIG] Move AIG dialect under Synth and remove AIG dialect, NFC by @uenoku in #8956
• [Arc] Add ExecuteOp by @fabianschuiki in #8949
• [ImportVerilog] Add support for materializing FixedSizeUnpackedArrayType as UnpackedArrayType. by @Scheremo in #8960
• [Synth] Implement basic canonicalization/folder to mig.maj_inv by @uenoku in #8959
• [Synth] Add support for mig.maj_inv in longest path analysis by @uenoku in #8965
• [Reduce] Various reducer improvements by @fabianschuiki in #8957
• [SV] Include CallInterface by @uenoku in #8966
• [Moore] Add builtin for $urandom by @Scheremo in #8968
• [ESI] Bump zlib tag by @mortbopet in #8963
• [ESI] Factor out inner execution in Simulator::run by @mortbopet in #8964
• [Synth] Add structural hashing pass for AIG/MIG operations by @uenoku in #8962
• [ConvertToArcs] Add llhd.combinational conversion by @fabianschuiki in #8950
• [Verif] handle self-referencing operations by @ollef in #8972
• [ArcToLLVM] Add arc.execute conversion by @fabianschuiki in #8951
• [AIG] feat : and_inv fold by @markram1729 in #8958
• [Moore] Add builtins for simulation time measurements by @Scheremo in #8970
• [ImportVerilog][Moore] Add support for %t format specifier, introduce moore.fmt.time by @Scheremo in #8979
• [FIRRTL] Emit fopen calls to get fd's not mcd's. by @dtzSiFive in #8981
• [FIRRTL] Add reduction that moves MustDedup onto children by @fabianschuiki in #8969
• [Moore] Add support for $random system task by @Scheremo in #8982
• [ESI] Add skid buffer to Cosim_Endpoint_ToHost by @teqdruid in #8983
• [ESI] Set '--output-split' for verilator compilation by @mortbopet in #8978
• [ESI] Librarify ESI cosim classes by @mortbopet in #8953
• [Datapath] Add product of sum partial product operator by @cowardsa in #8980
• [Moore] Add shortreal type, bit <-> real conversions by @Scheremo in #8985
• [ImportVerilog] Fix missing RValue conversion for struct_create by @Scheremo in #8988
• [Synth] Rename FanIn/FanOut StartPoint/EndPoint by @markram1729 in #8976
• [ESI2Phy] Adapt usage of rewriter to upcoming version. by @ingomueller-net in #8989
• [Synth][Strash] Use RegionDCE instead of UnusedOpPruner by @uenoku in #8990
• [Support] Add walkPostOrder and walkInversePostOrder to InstanceGraph by @fabianschuiki in #8974
• [FIRRTL] Handle ClassTypes properly in Dedup by @fabianschuiki in #8975
• [FIRRTL] Various small reduction pattern tweaks by @fabianschuiki in #8984
• [Moore][ImportVerilog] Add moore.fmt.string, support for $sformatf by @Scheremo in #8993
• Bump LLVM to 580860e8b7341783e8e53114f26b9a9659a3a3e1 by @fzi-hielscher in #8995
• [ImportVerilog][Bug] Fix single argument expressions in severity tasks by @Scheremo in #8998
• [LTL][ImportVerilog] Add support for $rose, $stable, $fell by @Scheremo in #8999
• [Synth] LowerWordsToBits: Improve scalability with bit-sensitive constprop by @uenoku in #8997
• [Arc] Add MergeTaps pass by @fzi-hielscher in #9000
• [Reduce] Various reduction tweaks by @fabianschuiki in #9004
• [FIRRTL] Add a missing unrealized conversion cast in LowerClasses by @fabianschuiki in #9005
• [Synth][LongestPathAnalysis] Remove hack for passing top module name through IR attribute by @uenoku in #9006
• [circt-verilog-lsp] Add definition and reference providers by @uenoku in #8280
• [circt-test] accept LoweringOptions to control the generated Verilog by @ollef in #9001
• [HWLegalizeModules] add disallowClockedAssertions lowering flag by @ollef in #9002
• [FIRRTL] Ensure all types and attributes are walkable by @fabianschuiki in #9007
• [build] Update Slang dependency properties before installing by @jmgorius in #9017
• [ESI] Allow single-file additions to SourceFiles by @mortbopet in #9019
• [Sim] Rename FormatLitOp to FormatLiteralOp, NFC by @fzi-hielscher in #9015
• [Datapath] Custom Partial Product Lowering for computing the Square of the input by @cowardsa in #9010
• [circt-verilog-lsp] Add support for package import indexing by @Scheremo in #9023
• [ESI] Route simulator compilation/exec output through callbacks by @mortbopet in #9009
• [Build] Set /utf-8 flag specifically for slang targets by @fzi-hielscher in #9027
• [ExportVerilog] Require $unsigned for outer-most expression in assignment by @uenoku in #9024

New Contributors

• @ollef made their first contribution in #8972
• @markram1729 made their first contribution in #8958
• @ingomueller-net made their first contribution in #8989
• @jmgorius made their first contribution in #9017

Full Changelog: firtool-1.131.0...firtool-1.132.0

This is a patch release that adds the -emit-chisel-asserts-as-sva to the 1.5 series of releases.

What's Changed

• [LowerToHW][firtool] Backport -emit-chisel-asserts-as-sva to 1.5 by @seldridge in #9028

Full Changelog: sifive/1/5/7...sifive/1/5/8