ih8sn allows you to modify system properties at runtime.

Mattermost documentation

RISC-V cryptography extensions standardisation work.

主要更新AX6！其他AX3600和AX9000暂时无更新，每个版本对应固件名称及大小不一样，看清楚下载。不搞多神秘什么本地编译啥的，涵盖的机型-AX6-AX3600-AX9000。部分插件源码均拉取原作者最新的。Boos4721源编译的固件特别说明： 管理地址：10.10.10.1 登陆密码：boos 无线密码：1234567890 新增恢复5.10内核固件的支持！目前仅AX6和AX3600…

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Freedom U540-C000 Bootloader Code

A directory of Western Digital’s RISC-V SweRV Cores

Generator Bootcamp Material: Learn Chisel the Right Way

A guide for getting the Toshiba Chromebook 2 running Linux natively! Please proceed to the wiki https://github.com/brendenyule/NativeToshibaCB2Guide/wiki

CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

⛔️ DEPRECATED - Ledger Live (Desktop)

Low-level Python interface to Sun Grid Engine

USB SPI programmer/debugger for CSR BlueCore bluetooth chips, based on FTDI USB to UART converter, for Linux and Windows

RTL, Cmodel, and testbench for NVDLA

GDB stub that allows debugging of embedded devices

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

The MyHDL development repository

Milandr MCU 1986x flashing with J-Link

Pure Python imaging library with Python 2.6, 2.7, 3.1+ support

OpenWRT buildroot for WITI board

Open Source Continuous File Synchronization

Linux Kernel for OpenPiton

Google Drive client for the commandline

Scala based HDL

Mirror of https://git.lede-project.org/?p=source.git Please send your PRs against this tree. They will be merged via staging trees and appear in this tree once the staging trees get merged back int…

ASUS RT-N56U/N65U/N14U/N11P/AC51U/AC54U/AC1200HP custom firmware