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  1. sg-76c61366 sg-76c61366 Public

  2. lab-riscv-asm lab-riscv-asm Public

    Lab work 1

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  3. lab_scr1_sim lab_scr1_sim Public

    Forked from v-crys/scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

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  4. systemverilog-homework systemverilog-homework Public

    Forked from chipdesignschool/systemverilog-homework

    SystemVerilog language-oriented exercises

    SystemVerilog