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1. scr1 scr1 Public

   Forked from syntacore/scr1

   SCR1 is a high-quality open-source RISC-V MCU core in Verilog

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2. RegBuilder RegBuilder Public

   Forked from Shmelnick/RegBuilder

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3. VerilogCodeECC VerilogCodeECC Public

   Forked from raya4213/VerilogCodeECC

   Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field

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4. verilog-mini-demo verilog-mini-demo Public

   Forked from ic7x24/verilog-mini-demo

   Verilog极简教程

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5. Verilog-Design-Examples Verilog-Design-Examples Public

   Forked from snbk001/Verilog-Design-Examples

   tbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bi…

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6. core_usb_cdc core_usb_cdc Public

   Forked from ultraembedded/core_usb_cdc

   Basic USB-CDC device core (Verilog)

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