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RTL Buddy

RTL Buddy mascot

RTL Buddy

Open-source tooling for SystemVerilog/Verilog design and verification —
built to work well for both humans and AI agents.

PyPI Docs License

RTL Buddy is an ecosystem of tools centered on rtl_buddy, a Python CLI that gives RTL projects a single, repeatable control plane for everyday design and verification work. It sits on top of the open-source tools your project already uses — Verilator, Yosys, OpenROAD, SymbiYosys, Surfer, Verible — giving you a cleaner interface, structured machine-readable output for CI and coding agents, and rich formatted output for people.

Start here

uv add rtl_buddy
uv run rb test basic        # run a single test
uv run rb regression        # run the full regression
uv run rb cdc -c cdc/sandbox/cdc.yaml

What it does


Simulation & Regression
rb test · rb regression

Waveform Debug
rb wave · rb hub

Synth · PnR · Power
rb synth · rb pnr · rb power

CDC Lint
rb cdc

Formal Verification
rb fpv

Mutation Testing
rb mut

AXI Profiling
rb axi-profile

Spec Traceability
rb spec

FPGA Implementation
rb fpga

Design-Space Exploration
rb xplr

CI & Agent Mode
JSONL logs · rb tool-check

Design philosophy

RTL Buddy is an experiment in agent-built EDA tooling — built by agents, for agents, with humans in the loop. The code, tests, and tooling across these repos are written largely by AI coding agents under human supervision, and the tools are designed first to be driven by agents: structured YAML config, machine-readable JSONL output, and explicit tool-readiness checks so an agent can plan, run, and interpret a full RTL flow on its own.

We're betting on speed. Letting agents do the building lets us move at a pace a hand-written toolchain of this scope simply can't — spanning simulation, synthesis, PnR, power, CDC, formal, mutation, profiling, and more, and growing fast.

We're equally blunt about the catch: agent-written code moves fast and breaks things. Gaps, rough edges, and the occasional wrong turn come with the territory. Our bet is that we can close them just as fast as we make them — with agents, backed by human review, regression suites, and the project template as a constant end-to-end check.

So treat this as living, breaking, fast-moving software. Pin your versions, expect things to change under you, and open issues when something cracks — that loop, agents fixing what agents built, is the project.

The ecosystem

Core tools

Repo What it does
rtl_buddy The CLI — tests, regressions, synthesis, PnR, power, coverage, and the coordination hub that ties the rest together
rtl-buddy-cdc Clock-domain-crossing lint engine (rb cdc)
rtl-buddy-view RTL hierarchy and connectivity visualization (rb hier)
rtl-buddy-axi-profiler AXI/APB/AHB interconnect performance profiler (rb axi-profile)
rtl-buddy-xeno SystemVerilog AST mutator powering mutation testing (rb mut) and CDC/FPV fuzz corpora
rtl-buddy-tools Pinned, validated macOS/Linux builds of every EDA tool rtl_buddy depends on

Editor integration

Repo What it does
rtl-buddy-nvim Neovim plugin for the RTL Buddy coordination hub

Vendored upstream tools

RTL Buddy maintains lightly-patched forks of several open-source EDA tools so its flows stay reproducible across platforms. Upstream is always the canonical source — these exist only to pin known-good builds and carry integration fixes.

yosys · yosys-slang · surfer · verilator · PeakRDL · coverview

Documentation

Full docs live at rtl-buddy.github.io/rtl_buddy.

License

RTL Buddy's first-party tools are released under the BSD-3-Clause license. Forked upstream projects retain their original licenses.

Popular repositories Loading

  1. rtl_buddy rtl_buddy Public

    RTL Buddy is a Python CLI for Verilog and SystemVerilog regression testing, Verilator and VCS simulation workflows, coverage, and YAML-based RTL verification automation.

    Python 3 2

  2. rtl-buddy-project-template rtl-buddy-project-template Public template

    Template project for the rtl_buddy tool

    SystemVerilog

  3. PeakRDL-regblock PeakRDL-regblock Public

    Forked from SystemRDL/PeakRDL-regblock

    Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

    Python

  4. PeakRDL PeakRDL Public

    Forked from SystemRDL/PeakRDL

    Control and status register code generator toolchain

    Python

  5. info-process info-process Public

    Forked from antmicro/info-process

    Python

  6. coverview coverview Public

    Forked from antmicro/coverview

    Coverview

    Vue

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Showing 10 of 17 repositories

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