Skip to content
View rvalles's full-sized avatar

Block or report rvalles

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

7 stars written in SystemVerilog
Clear filter

Send video/audio over HDMI on an FPGA

SystemVerilog 1,212 131 Updated Feb 3, 2024

A simple superscalar out-of-order RISC-V microprocessor

SystemVerilog 224 20 Updated Feb 24, 2025

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

SystemVerilog 192 27 Updated Nov 6, 2025

Tamagotchi P1 for Analogue Pocket and MiSTer

SystemVerilog 163 3 Updated May 19, 2024

FX68K 68000 cycle accurate SystemVerilog core

SystemVerilog 155 32 Updated Jun 1, 2021

MOS 6520 PIA / MOS 6522 VIA / MOS 6526/8520/8521 CIA replacement

SystemVerilog 48 5 Updated Jun 26, 2025

USB 2.0 FS Device controller IP core written in SystemVerilog

SystemVerilog 37 13 Updated Dec 2, 2018