Verilog Ethernet components for FPGA implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

An Open-source FPGA IP Generator

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Open source retro ISA video card

VRoom! RISC-V CPU

iCESugar FPGA Board (base on iCE40UP5k)

Minimax: a Compressed-First, Microcoded RISC-V CPU

Commodore 64 VIC-II 6567/6569 Replacement Project

Amiga Minimig ported to the Tang Nano 20k FPGA

Turbo9 - Pipelined 6809 Microprocessor IP

8MB Autoconfig FastRAM for Amiga 500/1000/2000/CDTV

4/8 MB Fast RAM Expansion for the Commodore Amiga 500

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

CPLD Replacement for A2000 Buster

Spitfire 500, A low-end 14 MHz Accelerator with IDE and 4/8 MB fast RAM for the Amiga 500.

W65C832 (32 bit 6502) in an FPGA.

This repository houses the ModRetro Chromatic's FPGA design files.

Integrated System for Enhancing VIC Output

A small 6502 system with MS BASIC in ROM

Re-coded Xilinx primitives for Verilator use

Atari ST/STe core for FPGAs

Verilog code to replace the Commodore SDMAC found in the A3000

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new a…

A ReAgnus MegaAChip PCB that takes a Gowin FPGA with embedded PSRAM, a PLCC-84 plug and FET level shifters.

An open source flicker fixer PCB for Amiga 1200 and 500