APB4 Watchdog Timer

wdg is a synthesizable APB4 watchdog timer intended for SoC supervision. The watchdog counter runs from an independent clock domain and remains alive while its reset request resets the system clock domain.

The version 2 interface provides:

• a 32-bit counter and 20-bit programmable prescaler;
• windowed service with early, malformed, and timeout failure detection;
• a sticky early-warning interrupt and a bounded system-reset request;
• a two-write service sequence and one-way configuration lock;
• optional debug-halt freeze;
• watchdog-reset cause and saturating reset-count retention;
• APB-to-watchdog clock-domain crossings with request/acknowledge mailboxes;
• hand-written RTL and C register definitions checked for parity.

This IP is suitable for commercial SoC integration, but it is not a certified functional-safety element. Integrators remain responsible for clock-failure monitoring, reset-tree analysis, diagnostic coverage, and product safety assessment.

• rtl/: package, interface, clock-domain bridge, register bank, and core.
• dv/unit/: asynchronous-clock APB unit test.
• formal/: SymbiYosys safety proof for the watchdog core.
• sw/: freestanding C register definitions, driver, and host tests.
• doc/: architecture, integration, verification, and safety collateral.
• config/ and scripts/: locked standalone development dependencies.

Use a sibling Common checkout or set COMMON_ROOT explicitly:

make doctor
make format-check register-check lint
make test synth formal

For a clean CI-equivalent environment:

python3 scripts/setup_dependencies.py --common \
  --tool verible --tool verilator --tool sv2v --tool iverilog \
  --tool yosys --tool sby --tool bitwuzla

The architectural contract and register ABI are specified in doc/datasheet.md.