Skip to content
View stevej's full-sized avatar

Block or report stevej

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Unlock 2 extra cores on the AMD BC-250

Python 123 14 Updated Jul 31, 2026

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short).

Verilog 250 25 Updated Aug 1, 2026

WallaBMC is a lightweight BMC for STM32 and similar class MCUs, with Web UI, Redfish, and HTTPS support. Based on Zephyr RTOS.

C 52 12 Updated May 31, 2026

Motorola 68000 interpreter, disassembler and assembler (code emitter)

Rust 30 4 Updated Jul 8, 2026

Suite of KLayout plugins to boost your layout productivity

10 4 Updated Aug 1, 2026

Motorola 680x0 emulator written in C

C 613 121 Updated Mar 8, 2026

Collateral for an AliExpress XCKU5P dev board

VHDL 18 Updated Apr 22, 2025

A configurable SRAM generator

Rust 67 8 Updated Jun 28, 2026

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

Scala 21 3 Updated May 12, 2025

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Shell 956 157 Updated Jul 31, 2026

Opensource DDR3 Controller

Verilog 466 73 Updated Jun 12, 2026
Verilog 29 1 Updated Jan 13, 2026

Information Repository for Plexus Unix computers like the Plexus P/20

C 63 8 Updated Jul 2, 2024

The next generation of OpenLane, rewritten from scratch with a modular architecture

Python 365 79 Updated Dec 2, 2025
Jupyter Notebook 175 29 Updated Jul 24, 2023

Learn, share and collaborate on ASIC design using open tools and technologies

Dockerfile 12 1 Updated Dec 27, 2020

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

Python 103 6 Updated May 16, 2023

8 Bit CPU in Verilog created for TinyTapeout09, based on SAP-1 design with added Programmer Module

Python 7 3 Updated Apr 20, 2025

build a toolchain for cross developement. Supports motorola m68k-elf, avr and arm-none-eabi

Shell 30 5 Updated May 25, 2026

Sail RISC-V model

Sail 744 279 Updated Jul 30, 2026

Hardware Description Languages

1,164 111 Updated Jul 9, 2026

Documentation for RTL-with-customcells to GDSII

Verilog 8 2 Updated Oct 25, 2023

RISC-V hypervisor written in Rust

Rust 370 38 Updated Dec 18, 2019

Get detailed, per-pod network metrics for export to prometheus.

Go 1 Updated Mar 14, 2022

XLS: Accelerated HW Synthesis

C++ 1,808 267 Updated Aug 1, 2026

An SVG rendering library.

Rust 3,978 328 Updated Aug 2, 2026

DNS flag day

JavaScript 149 39 Updated Oct 12, 2022
Rust 5 1 Updated Oct 1, 2025

A collection of innocent cubes, to freak out your engine, or not. If not you may receive the "deccer-cubes-approval" role on our discord."

56 6 Updated Jan 19, 2025
Next