Small accelerator design for machine learning

Bog as in: bog-standard, bogus or buggy. Playing around with OV2640 and FPGA based image processing.

RISC-V SoC on DE2-115: NEORV32 + 10 Wishbone peripherals + FreeRTOS + VGA/PS2/SDRAM + 22 CLI apps

Angular-based calculator for factory games like Factorio and Dyson Sphere Program

CAN FD IP Core in VHDL

Small Repository containing helpful material to develop programs for the NEORV32

🪐 Markdown with superpowers: from ideas to papers, presentations, websites, books, and knowledge bases.

NEORV32 RV32IMAC soft-core running nommu Linux with a 4×4 INT8 systolic array NPU on the Heijin AX301 board (Altera Cyclone IV EP4CE6).

Core-NPU is an Open-source Wishbone NPU developed in VHDL to accelerate common ML operations by performing them in hardware

Booting nommu Linux (kernel 6.6.83) on a NEORV32 RV32IMC soft-core FPGA

Cloneless1 is an open-source tamper-resistant cryptographic ASIC design

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:

Documentation of the RISC-V C API

ULX5M with GateMate with SDRAM

Latex source files of the open-source book FREE RANGE VHDL

RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.

What if we synthesize IEEE.float_pkg?

Running DOOM on the NEORV32 CPU

Library with VHDL cores implementing Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications such as APB, AHB, AXI, and AXI-Stream.

A GitHub template repository for quickly creating VHDL/FPGA projects with a standardized structure and preconfigured CI/CD workflows, including OSVVM support.

A custom FPGA-based fixed-point neural-network accelerator, integrated with a RISC-V soft-core, using VHDL, and bare-metal C.

Generate VHDL RTL that implements a register block from compiled SystemRDL input.

Control and status register code generator toolchain

picolibc - a C library designed for embedded 32- and 64- bit systems.

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin co…

Gamified compiler writing

Linux-only RV32IMA RISC-V CPU core with Sv32 MMU and SSTC

After reseting, when the NEORV32 bootloader is available over UART, will upload a neorv32_exe.bin

IEEE 754 single and double precision floating point library in systemverilog and vhdl

Baochip 1x Silicon