UVM Auto Generate ; Verify Project Build; Verilog Instance

uvm auto generator

The UVM written in Python

Verilog PCI express components

Python - 100天从新手到大师

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Lua Quick Start Guide, published by Packt

《labuladong的算法小抄》顺序阅读版

Crack LeetCode, not only how, but also why.

一步一步写MIPS CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

I was always intrigued whenever I see how someone can automate a task with a few lines of code. Here are some interesting Python scripts that lets you automate various daily tasks.

Bug-fix-only libev port of shadowsocks. Future development moved to shadowsocks-rust

Neural style in TensorFlow! 🎨

A curated list of awesome Machine Learning frameworks, libraries and software.

An opinionated list of Python frameworks, libraries, tools, and resources

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An absolute beginner's guide to Machine Learning and Image Classification with Neural Networks

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📗 The Beauty of Python Programming.

Be great at emacs in one year

lean & mean status/tabline for vim that's light as air

Vim配置，为python、go开发者打造的IDE。

A vim plugin to display the indention levels with thin vertical lines

爬虫，抓取某电影聚合网站电影信息、磁力链接下载地址

A code-completion engine for Vim

my vim config to share amongst my machines

vim配置

Bugs, suggestions or free discussions about the minimal markdown editor — Typora