关于uart_rx模块中FIFO状态机（wdata_state）的问题 #2

wdata_state 为什么需要2‘b10状态，直接从2’b01跳转到2‘b00不可以吗？

always@(posedge clk or negedge rst_) begin
if(!rst_) begin
rx_ack <= 1'b0;
rx_fifo_winc <= 1'b0;
wdata_state <= 2'b0;
end
else begin
case(wdata_state)
2'b00: begin
if(!rx_fifo_wfull && rx_start_delay2) begin
rx_ack <= 1'b1;
rx_fifo_winc <= 1'b1;
wdata_state <= 2'b01;
end
end
2'b01: begin
rx_fifo_winc <= 1'b0;
if(!rx_start_delay2) begin
rx_ack <= 1'b0;
wdata_state <= 2'b10;
end
end
2'b10: begin
wdata_state <= 2'b0;
end
endcase
end
end