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IEEE 754 single and double precision floating point library in systemverilog and vhdl
VHDL 82 12
IEEE 754 single precision floating point library in systemverilog and vhdl
VHDL 42 4
Wallace and Dadda tree multiplier generator in vhdl and verilog
C++ 14 4
6-stage dual-issue in-order superscalar risc-v cpu
SystemVerilog 14 5
2-stage single-issue in-order scalar risc-v cpu
SystemVerilog 6 3
8-stage quad-issue out-of-order superscalar risc-v cpu
SystemVerilog 1
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