Interests: speculative superscalar out-of-order cpu microarch, ISA design, memory system, ...
VLSI/ASIC, sync and async (dynamic) logic
- Milpitas, CA, USA
-
09:25
(UTC -08:00) - https://chaos.social/@tommythorn
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10
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written in HTML
Clear filter
Style your webpage like Edward Tufte’s handouts.
ECP5 breakout board in a feather physical format
skypjack on software
Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site
Content and code from Haskell Embedded blag