Simmerv is a RISC-V SoC emulator written in Rust and compilable to WebAssembly. It began as a fork of Takahiro's riscv-rust emulator, but has by now been extensively rewritten, making it far more complete and much faster. Ultimately, we expect it to become substantially faster, but this work is delayed until we are able to run standard benchmarks and off-the-shelf Linux distributions.

You can run Linux on the emulator in your browser: online demo is here

• Emulates RISC-V RV64GC_Zba_Zbb_Zbc_Zbs_Zicond_Zfhmin_Svinval_Svade_Svpbmt_Sstc_Zicbom_Zicbop_Zicboz_Zihpm (RVA22) processor and peripheral devices (CLINT, PLIC, NS16550A UART, virtio block device, and VirtIO ethernet)
• Targets native and WASM
• Snapshots
• Speedometer

• RV64IMAC
• RV64FD
• RV64Zifencei
• RV64Zicsr
• Zba, Zbb, Zbc, Zbs ("B" extension)
• Zicond
• Zfhmin (half-precision float conversions)
• Zihpm (hardware performance counters)
• Zicbom, Zicbop, Zicboz (cache block operations)
• Svinval (fine-grained TLB invalidation)
• Svade (hardware A/D fault-on-access)
• Sstc (stimecmp/menvcfg timer compare)
• Sv39, Sv48, Sv57
• Svpbmt (page-based memory types; PTEs accepted, no caches to model)
• Privileged Spec 1.12 (mcounteren/scounteren, senvcfg, PMP stub with 0 entries)
• Svnapot
• [-] PMP enforcement (0 entries implemented; all accesses permitted)

The emulator supports all instructions listed above.

• Passes all riscof (RISC-V Architectural Tests) for RV64IMC
• Boots Buildroot, Debian Trixie, Ubuntu
• Linux OpenSBI and legacy BBL boot support

VERY IMPORTANT: images are stored with git LFS. Install LFS (don't forget git lfs install also) and recheckout if needed. Otherwise the images will be small files with LFS pointers.

$ cargo r -r -- linux/fw_payload.bin,0x80000000 -f linux/rootfs.img

or

$ cargo r -r -- -c linux/opensbi/fw_jump.elf,0x80000000 linux/vmlinux,0x80200000 -f linux/rootfs.img

Allocate 2 GiB, use a device tree with initramfs at 0xa0000000 and load the initrd2+gdb.cpio binary at that address.

$ (cd linux;cargo r -r -- -m 2048 -d with-initrd.dtb fw_payload.bin,0x80000000 initrd2+gdb.cpio,0xa0000000)

$ ./run-riscv-tests.sh

See wasm/web

See wasm/npm

Running 64-bit RISC-V Linux on QEMU

• RISC-V ISA
• Virtio Device
• UART
• CLINT, PLIC (SiFive E31 Manual)
• SiFive Interrupt Cookbook