PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

A toy L4 load balancer running on FPGA

Verilog model and simulator (emulator) for the Gigatron TTL microcomputer .

SoCeteer - A framework for designing and running RISC-V-based SoCs on FPGA and in Simulation, built on top of Chisel.

C++ objects to help verilator simulations

Development of a minimal RISC-V System on Chip and integration with a computational accelerator written in Verilog. It serves as an example of a minimal architecture and as a foundation for future expansions (real hardware accelerators for scientific computing and AI).