An abstraction library for interfacing EDA tools

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Extended and external tests for Verilator testing

👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)

SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.

Python/PyPI wrapper for Verilator

🪀 Tool to play with HDL (inspired by EdaPlayground)

Tests your ECE 320 Single Cycle RISC-V Processor: Up to PD5

Provide a basic structure to starts a Verilog or Systemverilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)

TB_LINT - Modular Linting Framework

Cross-platform tool for students to simulate Verilog designs

Python AES

EDA server for simulating and validating hardware designs described in Verilog/SystemVerilog, focusing on functionality, performance, area, and power evaluation.

FORCE AI: Fast Optimization for Resource-Constrained Efficient AI Inference