xrt
Here are 7 public repositories matching this topic...
High-throughput Sparse Matrix–Vector Multiply (SPMV) accelerator for the Xilinx Alveo U280, redesigned from Serpens A16 into a fully Vitis HLS dataflow kernel with 24 HBM channels and improved memory and parallelism.
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Dec 3, 2025 - C++
First documented end-to-end PL + AIE-ML + PS pipeline on Versal AI Edge XCVE2302 (VD100). MA crossover trading signal via HLS DMA + AIE graph + XRT host app. No VCK190. No MATLAB. Ethereum audit log on Hardhat.
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Apr 11, 2026 - C++
PS userspace XRT application for the VD100 MA Crossover AIE-ML pipeline. Drives mm2s/s2mm HLS kernels and mygraph via XRT 2025.2 on XCVE2302. Includes golden test vector validation and XRT lifecycle performance analysis.
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Apr 14, 2026 - C++
AIE-ML moving average crossover kernel for VD100 (XCVE2302). Dual MA (fast 10 / slow 50 period), BUY/SELL/HOLD signal. 56 int32 samples/iteration via HLS DMA. Used in vd100-aie-pipeline. Vitis 2025.2.
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Apr 14, 2026 - C++
Implementation of the Phylogenetic Liklihood Function for the AMD Versal architecture (FPGA and AI processors on same SoC).
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Nov 27, 2024 - C++
Live Binance WebSocket feed → MA crossover signal → Ethereum smart contract on Versal AI Edge XCVE2302 (VD100). SW mode: 1440ns on A72. AIE-ML v2 XRT pipeline integrated and benchmarked. XRT architectural findings documented.
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Apr 13, 2026 - C++
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