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AnyDSL / flower

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A Comprehensive Dataflow Compiler for High-Level Synthesis

fpga hls image-processing high-performance-computing dataflow xilinx-fpga high-level-synthesis intel-fpga xrt vitis

Updated Sep 14, 2025
CMake

adilsondias-engineer / vd100_ma_system_project

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Vitis 2025.2 system project for VD100 (XCVE2302) — v++ link + package for AIE-ML v2 + HLS kernel integration. Produces aie.xclbin and BOOT.BIN CDO artifacts. Reusable: swap AIE kernel or add HLS kernels without new project.

fpga hls amd xilinx versal xrt bootgen vitis xcve2302 vd100 aie-ml xclbin mm2s s2mm

Updated Apr 11, 2026
CMake

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xrt

Here are 2 public repositories matching this topic...

AnyDSL / flower

adilsondias-engineer / vd100_ma_system_project

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