axi

Here are 6 public repositories matching this topic...

SystemRDL / PeakRDL

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Updated Mar 24, 2026
Python

hdl-registers / hdl-registers

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An open-source HDL register code generator fast enough to run in real time.

python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface

Updated Apr 6, 2026
Python

bugratufan / axion-hdl

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Axion-HDL: Automated AXI Register Space Generation Tool

Updated Mar 25, 2026
Python

Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking testbenches with VCD waveform output are included. Hardware tested.

fpga vhdl verilog crc vivado ghdl yosys iverilog axi

Updated Mar 23, 2026
Python

aignacio / jtag_axi

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JTAG to AXI master

jtag axi jtag-adapter

Updated Dec 14, 2025
Python

mjh-design / verilog-axis

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Verilog AXI stream components for FPGA implementation

ip axi

Updated Feb 17, 2023
Python

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axi

Here are 6 public repositories matching this topic...

SystemRDL / PeakRDL

hdl-registers / hdl-registers

bugratufan / axion-hdl

bard0-design / crcZero

aignacio / jtag_axi

mjh-design / verilog-axis

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