AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
-
Updated
Oct 27, 2025 - SystemVerilog
#
axi
Here are 19 public repositories matching this topic...
Network on Chip Implementation written in SytemVerilog
-
Updated
Aug 27, 2022 - SystemVerilog
Simple single-port AXI memory interface
-
Updated
Jun 7, 2024 - SystemVerilog
Common SystemVerilog RTL modules for RgGen
-
Updated
Sep 5, 2025 - SystemVerilog
Formal AXI verification properties from the eXpect framework for secure SoC validation
verification eda systemverilog soc formal-verification axi amba hardware-security questa axi4 axi4-lite hardware-design
-
Updated
Oct 28, 2024 - SystemVerilog
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
-
Updated
Sep 13, 2025 - SystemVerilog
-
Updated
Jun 5, 2017 - SystemVerilog
Synchronous and Asynchronous FIFO with AXI interface
-
Updated
Nov 20, 2019 - SystemVerilog
Реализация AXI интерфейса на SystemVerilog
-
Updated
Jul 25, 2024 - SystemVerilog
Knowledge hub for digital interfaces
-
Updated
Apr 23, 2025 - SystemVerilog
Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.
systemverilog axi uvm-verification axi-uvc axi-verification-using-uvm axi-protocol axi-protocol-verification-using-uvm axi-uvm-project
-
Updated
Sep 24, 2025 - SystemVerilog
Improve this page
Add a description, image, and links to the axi topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the axi topic, visit your repo's landing page and select "manage topics."