Реализация AXI интерфейса на SystemVerilog
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Jul 25, 2024 - SystemVerilog
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axi
Here are 19 public repositories matching this topic...
Knowledge hub for digital interfaces
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Apr 23, 2025 - SystemVerilog
Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.
systemverilog axi uvm-verification axi-uvc axi-verification-using-uvm axi-protocol axi-protocol-verification-using-uvm axi-uvm-project
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Sep 24, 2025 - SystemVerilog
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Jun 5, 2017 - SystemVerilog
Synchronous and Asynchronous FIFO with AXI interface
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Nov 20, 2019 - SystemVerilog
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
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Sep 13, 2025 - SystemVerilog
Formal AXI verification properties from the eXpect framework for secure SoC validation
verification eda systemverilog soc formal-verification axi amba hardware-security questa axi4 axi4-lite hardware-design
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Oct 28, 2024 - SystemVerilog
Common SystemVerilog RTL modules for RgGen
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Sep 5, 2025 - SystemVerilog
Simple single-port AXI memory interface
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Jun 7, 2024 - SystemVerilog
Network on Chip Implementation written in SytemVerilog
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Aug 27, 2022 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Oct 27, 2025 - SystemVerilog
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