Asynchronous FIFO for transferring data between two asynchronous clock domains
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Jun 3, 2016 - Verilog
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clock-domain-crossing
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FIFO implementation with different clock domains for read and write.
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Aug 17, 2021 - Verilog
RTL designs and simulations for FIFO buffers (Synchronous & Asynchronous) in Verilog, targeting robust data handling architectures.
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May 18, 2025 - Verilog
Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.
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Aug 9, 2025 - Verilog
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