Hexadecimal 7 segment display
-
Updated
Aug 1, 2020 - VHDL
#
logic-design
Here are 9 public repositories matching this topic...
A continuous state diagram that outputs 1 when it receives an even number of 0s or even number of 1’s.
-
Updated
Feb 20, 2023 - VHDL
4 bit ripple adder, which adds 2 4-bit inputs introducing sum and carry signals. Implement the following modules: 1. Half adder. 2. Full adder using the half adder. 3. 4-bit ripple adder/subtractor using the full adder.
-
Updated
Feb 20, 2023 - VHDL
Repositorio del trabajo practico de la asignatura de Diseño Logico de la UNTREF, 2024C2
-
Updated
Jul 16, 2025 - VHDL
Project for the Reti Logiche Course at @POLIMI, instructed by Prof. Gianluca Palermo during the academic year 2022/23
-
Updated
Mar 10, 2024 - VHDL
This repository contains all my VHDL codes and projects. Feel free to use them however you like. I hope that you like them and that you find them educational/helpful. Feel free to connect with me on LinkedIn!
-
Updated
Mar 25, 2021 - VHDL
Improve this page
Add a description, image, and links to the logic-design topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the logic-design topic, visit your repo's landing page and select "manage topics."