This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

Combinational Multiplier Using verilog

Implementation of Texas Hold'em Poker on Verilog(Basys3 FGPA)

EECS207001

2021 Fall EECS-2070 by Prof. 李濬屹 Team37 with @schdoel

Carry Select Adder Using verilog

this is a college project of making SPI interface using verilog

A carry select adder is an arithmetic combinational logic circuit which adds two N- bit binary numbers and outputs their N-bit binary sum and a 1-bit carry.

Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog

A digital design for the SPI protocol, delivered as a project for the logic design course

Logic Design Laboratory

MK-LMC SIGANFU Tactical Power Armor - Final Verilog Project of Logic Design

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

Using a linear feedback shift register (LFSR), design a pseudorandom binary sequence (PRBS) generator.

11020EECS101002

Master-Slave Interface.

VARILAG LAGIK

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀