A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

Implementation of Texas Hold'em Poker on Verilog(Basys3 FGPA)

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

Quartus Lab assignments of NTU EE's switching circuit and logic design course (2023 fall).

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

🍟 Logic Design Verilog practice

MK-LMC SIGANFU Tactical Power Armor - Final Verilog Project of Logic Design

Master-Slave Interface.

2021 Fall EECS-2070 by Prof. 李濬屹 Team37 with @schdoel

EECS207001

11020EECS101002

this is a college project of making SPI interface using verilog

modelled encryption-decryption module using verilog. Given a text file, it can be encrypted using encryptor and can be decrypted later using decryptor.

Combinational Multiplier Using verilog

Carry Select Adder Using verilog

A digital design for the SPI protocol, delivered as a project for the logic design course

VARILAG LAGIK