Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

MK-LMC SIGANFU Tactical Power Armor - Final Verilog Project of Logic Design

EECS207001

Carry Select Adder Using verilog

2021 Fall EECS-2070 by Prof. 李濬屹 Team37 with @schdoel

Using a linear feedback shift register (LFSR), design a pseudorandom binary sequence (PRBS) generator.

11020EECS101002

Master-Slave Interface.

Combinational Multiplier Using verilog

VARILAG LAGIK

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

Game built using Logic and Verilog on a BASYS2 board.

this is a college project of making SPI interface using verilog

Implementation of Texas Hold'em Poker on Verilog(Basys3 FGPA)

Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog

Quartus Lab assignments of NTU EE's switching circuit and logic design course (2023 fall).

🍟 Logic Design Verilog practice

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

A carry select adder is an arithmetic combinational logic circuit which adds two N- bit binary numbers and outputs their N-bit binary sum and a 1-bit carry.

modelled encryption-decryption module using verilog. Given a text file, it can be encrypted using encryptor and can be decrypted later using decryptor.