🖥️ A 32-bit 5-stage scalar pipelined RISC-V processor that follows the RV32I ISA specification (ECE 411 Final Project).
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May 14, 2021 - Verilog
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risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
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Oct 10, 2025 - Verilog
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Jun 24, 2024 - Verilog
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
c assembly spike verilog gtkwave soc yosys risc-v iverilog gate-level-simulation hardware-design chipcron
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May 8, 2024 - Verilog
RISC-V pipeline processor: A high-performance, open-source CPU design implementing RISC-V architecture with efficient instruction pipeline execution.
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Mar 6, 2025 - Verilog
A pipelined RISC processor implemented in Verilog with hazard detection and data forwarding units.
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Jun 25, 2025 - Verilog
Emulation, implementation and verification of RISC-V core with I,M and Zbb extensions
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Sep 27, 2024 - Verilog
8-bit RISC ASIP for Stepper Motor Controller with both full and half step capabilities. Implemented in Verilog HDL.
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Apr 7, 2025 - Verilog
Single-cycle RISC-V processor in verilog, supporting the RV32I ISA
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May 30, 2024 - Verilog
A 32 bit RISC-V pipeline processor with forwarding unit
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Jul 20, 2025 - Verilog
This is a Single Cycle RISC-V processor implemented in verilog
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Jul 19, 2023 - Verilog
verilog model of a 32 bit RISC-V processor core supporting the RV32I instruction set
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Feb 12, 2024 - Verilog
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
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Mar 24, 2021 - Verilog
Single Cycle Non-Pipelined Processor for RV32I.
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Apr 13, 2025 - Verilog
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