Verilog implementations of single-cycle, multi-cycle and pipelined RISC-V CPUs.

Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

A computer engineering student created performance-optimized RISC-V processor implementation using the ZYNQ 7000 Series Z7-20 FPGA, including intelligent power management and adaptive branch prediction along with statistics. Coded in Verilog-HDL with AMD Vivado.

adapted small fpga and portability any device RISC-V core

Материалы для курсов по проектированию цифровых вычислительных систем

The aim of this study is to design and implement a RISC-V core with a pipelined architecture in Verilog HDL. While the core design has been successfully implemented, the hazard management unit remains under development. This article details the implementation approach, the challenges faced, and the results achieved thus far.

1131 NTU CSIE Computer Architecture Homework

3-stage RV32IMACZb* processor with debug

A 16-bit Instruction Set Architecture.

RISC-V single cycle CPU supporting RV32I instruction set (limited). Designed following the textbook "Digital Design and Computer Architecture RISC-V Editio" by Sarah L. Harris and David Money Harris. The CPU as it is proposed here is not fully compliant with official RISC-V specifications.

這是一個以 RISC-V ISA 為基礎的專題，除了這份專案的內容以外，以下也包含相關的學習紀錄

RISC-V soft-core microcontroller for FPGA implementation

A rebuild of RISC I, improved with RISC-V features, focused in didactic and built in Logisim Evolution

SERV - The SErial RISC-V CPU

RISC-V CORE DESIGN USING RV32I BASE ISA

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

Updating and Verifying Cal Poly's RV32I_Zicsr "Otter" Core

A 32-bit single-cycle RISC-V processor implemented in Verilog, capable of executing R-type, I-type, Load (LW), Store (SW), and Branch (BEQ) instructions.

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.